[PATCH 07/12] RISC-V: RV32F Support

[Joseph Myers]

On Wed, 14 Jun 2017, Palmer Dabbelt wrote:

> diff --git a/sysdeps/riscv/rvf/fedisblxcpt.c b/sysdeps/riscv/rvf/fedisblxcpt.c
> new file mode 100644
> index 0000000000..89434de352
> --- /dev/null
> +++ b/sysdeps/riscv/rvf/fedisblxcpt.c
> @@ -0,0 +1,29 @@

You could just use the generic math/ version here.

> diff --git a/sysdeps/riscv/rvf/feenablxcpt.c b/sysdeps/riscv/rvf/feenablxcpt.c
> new file mode 100644
> index 0000000000..e664a2fb3c
> --- /dev/null
> +++ b/sysdeps/riscv/rvf/feenablxcpt.c
> @@ -0,0 +1,29 @@

Likewise, but if you don't, at least follow its error handling rules.

> diff --git a/sysdeps/riscv/rvf/fegetexcept.c b/sysdeps/riscv/rvf/fegetexcept.c
> new file mode 100644
> index 0000000000..00dafd96fb
> --- /dev/null
> +++ b/sysdeps/riscv/rvf/fegetexcept.c

Likewise.

You seem to be missing implementations of the fesetexcept, fegetmode and 
fesetmode functions, new in 2.25 and generally needing 
architecture-specific implementations.  (Whereas the generic 
fetestexceptflag is fine for most architectures.)

> diff --git a/sysdeps/riscv/rvf/s_ceilf.c b/sysdeps/riscv/rvf/s_ceilf.c
> new file mode 100644
> index 0000000000..c168f5f93b
> --- /dev/null
> +++ b/sysdeps/riscv/rvf/s_ceilf.c

Remark: I think you could implement roundevenf for RISC-V in a similar way 
to the other round-to-integer functions, if that's beneficial.

> diff --git a/sysdeps/riscv/rvf/s_fabsf.c b/sysdeps/riscv/rvf/s_fabsf.c

If the generic sysdeps/ieee754/flt-32/s_fabsf.c, using __builtin_fabsf, 
doesn't generate the same code, that's a problem with your GCC port and 
should be addressed there rather than adding s_fabsf.c for this port.

-- 
Joseph S. Myers
joseph@codesourcery.com