[PATCH v2] powerpc: add sysconf support for cache geometries

[Tulio Magno Quites Machado Filho]

Tulio Magno Quites Machado Filho <tuliom@linux.vnet.ibm.com> writes:

> Paul Clarke <pc@us.ibm.com> writes:
>
>> There is currently no "cross-platform" (x86 and POWER) support for
>> determining the cacheline size.
>>
>> This patch adds support to sysconf() to correctly report cacheline sizes
>> based on the information in the auxilliary vector.
>>
>> Thus, using sysconf() is a cross-platform (x86 and POWER) solution for
>> determining cacheline sizes.
>>
>> Support is added (on powerpc) for:
>> _SC_LEVEL1_ICACHE_SIZE _SC_LEVEL1_ICACHE_ASSOC _SC_LEVEL1_ICACHE_LINESIZE
>> _SC_LEVEL1_DCACHE_SIZE _SC_LEVEL1_DCACHE_ASSOC _SC_LEVEL1_DCACHE_LINESIZE
>> _SC_LEVEL2_CACHE_SIZE  _SC_LEVEL2_CACHE_ASSOC  _SC_LEVEL2_CACHE_LINESIZE
>> _SC_LEVEL3_CACHE_SIZE  _SC_LEVEL3_CACHE_ASSOC  _SC_LEVEL3_CACHE_LINESIZE
>>
>> 2017-04-28  Paul A. Clarke  <pc@us.ibm.com>
>>
>> 	* sysdeps/unix/sysv/linux/powerpc/sysconf.c: New file.
>> 	Add powerpc-specific overrides for L1, L2, L3 CACHE_SIZEs,
>> 	CACHE_ASSOCs, and CACHE_LINESIZEs, retrieving from auxv.
>> 	* sysdeps/unix/sysv/linux/powerpc/test-powerpc-linux-sysconf.c:
>> 	New file.  Invoke newly supported sysconf values for powerpc,
>> 	and report results.  If none are supported, report so.
>> 	* sysdeps/unix/sysv/linux/powerpc/Makefile (tests):  Add new test,
>> 	tst-sysconf.
>
> The patch looks good except for a small issue.
>
> You need to bypass the PLT.  The problem is that neither getauxval()
> nor __getauxval() provide this for you.
>
> I'm sending a patch to treat this.

Pushed with this fix as cdfbe5037f2f67bf5f560b73732b69d0fabe2314.

-- 
Tulio Magno