[PATCH x86_64][BZ #20139] Don't allow configure with not supporting AVX512 assembler w/o --disable-avx512.

[H.J. Lu]

On Thu, Jun 30, 2016 at 4:15 AM, Florian Weimer <fweimer@redhat.com> wrote:
> On 06/29/2016 11:45 PM, H.J. Lu wrote:
>>
>> Subject: [PATCH] Require binutils 2.24 to build x86-64 glibc
>
>
> Please put [BZ #20139] at the end of the first line.

What do you mean by that?  My ChangeLog entries are

                 [BZ #20139]
                 * config.h.in (HAVE_AVX512_ASM_SUPPORT): Renamed to ...
                 (HAVE_AVX512DQ_ASM_SUPPORT): This.

It looks normal to me.

>
>> If assembler doesn't support , _dl_runtime_resolve_avx is used
>> to save the first 8 vector registers, which only saves the lower 256
>> bits of vector register, for lazy binding.  When it is called on AVX512
>> platform, the upper 256 bits of ZMM registers are clobbered.  Parameters
>> passed in ZMM registers will be wrong when the function is called the
>> first time.  This patch requires binutils 2.24, whose assembler can store
>> and load ZMM registers, to build x86-64 glibc.  Since mathvec library
>> needs assembler support for AVX512DQ,  we disable mathvec if assembler
>> doesn't support AVX512DQ.
>
>
> The commit message seems to be inconsistent.  Should the “AVX512DQ” on the
> first line actually be “AVX512F”?
>

Currently we check assembler support for AVX512DQ before enabling AVX512.
If assembler doesn't support AVX512DQ, we won't save ZMM registers even
though AVX512F is sufficient.

Here is the patch with updated commit message, including only disabling
the AVX512DQ part of mathvec without AVX512DQ.

OK for master?

-- 
H.J.
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