Malloc improvements

[Anton Blanchard]

Hi Florian.

> x86_64 checks __libc_multiple_threads and avoids atomics if possible. 
> Do you already do this in POWER?

x86 has CISCy instructions that do a local atomic increment/decrement,
and I suspect they use that in the single threaded case. We do not have
instructions like that on PowerPC, and it presents an issue for signals.

I think we got resistance when we suggested using load/add/store
instructions in single threaded mode on PowerPC because it made the
async signal situation somewhat worse. Of course malloc is not defined
to be async signal safe, and I bet there are places we fall apart today.
Perhaps we can revisit this now we have an unlocked per thread cache in
DJ's branch.

Anton