Adding cache shape info to powerpc

[Benjamin Herrenschmidt]

Hi !

So there are pending requests to provide cache shape/geometry
information to user space via the aux vectors.

This is done today by Alpha and SH using these:

/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains
   log2 of line size; mask those to get cache size.  */
#define AT_L1I_CACHESHAPEÂ Â Â Â Â Â Â 34
#define AT_L1D_CACHESHAPEÂ Â Â Â Â Â Â 35
#define AT_L2_CACHESHAPEÂ Â Â Â Â Â Â Â 36
#define AT_L3_CACHESHAPEÂ Â Â Â Â Â Â Â 37

I have written some kernel code to do the same on powerpc, however I had
to change the format of the entries. 4 bits isn't sufficient to represent
modern cache associativities on some server chips.

I've chosen this format. Is that ok with the community ? Can I still use
the same AT_* vector numbers or should I create new ones ?

/* More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
   value is -1, then the cache doesn't exist or information isn't
   availble.  Otherwise:

      bit 0-9:    Cache set-associativity 0 means fully associative.
      bit 10-13:  Log2 of cacheline size.
      bit 14-31:  Size of the entire cache >> 10.
      bit 32-39:  [64-bit only] more bits for total cache size.
      bit 40-63:  Reserved

   If any of the fields is all 1's, then that field isn't available.

    WARNING: The cache *line* size can be different from the cache *block*
             size. The latter, represented by vectors 19,20,21, is the size
             used by the cache management instructions such as dcbz. The
             cache line size on the other hand is the real HW line size
             for a given cache level which might be different and should
             only be used for performance related tuning
*/

#define AT_L1I_CACHESHAPE       34
#define AT_L1D_CACHESHAPE       35
#define AT_L2_CACHESHAPE        36
#define AT_L3_CACHESHAPE        37

Cheers,
Ben.