[PATCHv2] powerpc: Spinlock optimization and cleanup

[Steven Munroe]

On Thu, 2015-10-01 at 10:18 +0100, Szabolcs Nagy wrote:
> On 30/09/15 17:28, Paul E. Murphy wrote:
> >
> > ---8<---
> > This patch optimizes powerpc spinlock implementation by:
> >
> ...
> 
> The glibc pthread spinlock semantics is weaker than what
> posix requires, I'm wondering if this is expected to stay
> or glibc might want to switch to stronger semantics.
> 
Since when? Include the text the requires this?

> is it worthwhile to add optimized asm with weak semantics
> for other targets that currently use the generic c code?
> 
> (the issue is that for correct pthread_spin_trylock behavior
> the lock should be seqcst instead of acquire and the unlock
> should be release instead of barrier+store otherwise trylock
> can spuriously report locked state).
> 

Paul patch already changes pthread_spin_unlock to atomic_store_release,
which will generate lwsync/stw.

But I don't think anyone wants or need pthread_spin_lock to be seqcst.

Also as the acquire sequence used in Paul patch is a full "import
barrier", it is sufficient for the critical region.

Read PowerISA-2.07B BookII Appendix B Programming Examples for Shared
Storage, Section B.2.1 Lock Acquisition and Import Barriers.

Which specifically say that a hwsync is not required if the acquire
import barrier is used. And this sequence will perform better.