[PATCH] powerpc: Spinlock optimization and cleanup

[Richard Henderson]

On 02/27/2015 06:57 AM, Adhemerval Zanella wrote:
> We already have support for EH hint in LL/SC instruction for powerpc.  The trick
> in this algorithm is it does not really fix in current atomic semantics we have
> so far, as '__arch_compare_and_exchange_val_32_acq' issues an 'isync' in either
> fail or succeed case.  The trick in this case is just to emit the 'isync' just
> after the stcx. instruction.  Basically the idea is to loop over checking
> when lock is release using default loads 'inside' the CAS-acquire.  Suggestions?

This does sound like the two memory model inputs to the builtin
__atomic_compare_and_exchange_n: one for the succeed case and
one for the fail case.



r~