[PATCH][RFC] Fix SPARC atomic_write_barrier.

[Torvald Riegel]

This patch changes SPARC write barriers to be just release barriers.  I
haven't tested this, so this is based on my understanding of the SPARC
memory model (TSO).

For a release barrier, we have code like
  foo = 1;
  atomic_write_barrier ();
  release_flag = 1;
and release_flag could also be a spinlock unlock, for example.

So we want to prevent store/store and load/store reordering, so that the
release_flag assigment is the "last" thing.

Previously, the write barriers prevented -- AFAIU SPARC assembly --
store/load reordering, which is what you'd need a full barrier for on
TSO (e.g., consider Dekker synchronization).  The other kinds of
reordering barriers (e.g., load/store) are implicit on TSO (as on x86).
Thus, the change doesn't fix a correctness issue (at least if using
TSO!) but just a performance issue.

Could someone who cares about SPARC please review and test this?
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