[PATCH 0/3] Improve ARM atomic performance for malloc

[Will Newton]

The intention of this series is to improve the performance of ARM
atomics and hence malloc.

The first patch adds a malloc microbenchmark which is pretty much
the same code that I posted earlier in the year but with the
support for multiple threads taken out. The threaded aspect of the
benchmark appeared to be an area of contention so hopefully this
makes things simpler.

The second patch widens the range of supported atomic operations
in the ARM port which improves the generated code sequences for
things like atomic add, or and and.

The third patch which can be considered really more of an RFC
implements the single-threaded atomic optimization similarly to
the implementation for Power that was posted back in August.
There is a small performance gain at the cost of some complexity so
I wonder whether this optimization is really worth it, I would
be interested in people's opinions on that.

The resulting atomic.h is hopefully somewhere close to a generic
implementation based on the gcc intrinsics so could potentially
be used as a base for a generic header.

Will Newton (3):
  benchtests: Add malloc microbenchmark
  sysdeps/arm/bits/atomic.h: Add a wider range of atomic operations
  sysdeps/arm/bits/atomic.h: Use relaxed atomics for catomic_*

 benchtests/Makefile       |   2 +-
 benchtests/bench-malloc.c | 219 ++++++++++++++++++++++++++++++++++++++++
 sysdeps/arm/bits/atomic.h | 248 +++++++++++++++++++++++++++++++++++++---------
 3 files changed, 420 insertions(+), 49 deletions(-)
 create mode 100644 benchtests/bench-malloc.c

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1.9.3