PowerPC: memset optimization for POWER8/PPC64

[Richard Henderson]

On 07/21/2014 03:17 AM, Adhemerval Zanella wrote:
> In fact, in this case it will need to write 1-15 bytes based 'clrldi' result.  And
> for POWER8, although unaligned store are handled with performance equivalence of
> aligned ones, some cases POWER8 will either:
> 
> * force break unaligned in multiple internal operations (misaligned flushes in a
>   crossing 128-byte cache-line boundaries and storing a 4KB small page boundary);

This, I assume isn't actually a big deal.  Internal operations floating around
the execute queue are certainly better than the pipeline flush caused by a
mis-predicted branch.

> * trigger an alignment interrupt in caching-inhibited storage.  This is why I have
>   pushed the patch 87868c2418fb74357757e3b739ce5b76b17a8929 on memcpy: if you use
>   memcpy on a DMA mapped memory (from a GPU for instance), doing *any* unaligned
>   store will result in alignment interrupt.  And I got reports that the X server
>   is doing it (that's why the patch).

However, this is certainly a good reason.  Thanks for the pointer.


r~