[PATCH 13/13] AArch64: Cleanup fenv implementation

[Wilco Dijkstra]

ping

> -----Original Message-----
> From: Wilco Dijkstra [mailto:wdijkstr@arm.com]
> Sent: 23 October 2014 18:37
> To: 'libc-alpha@sourceware.org'
> Subject: [PATCH 13/13] AArch64: Cleanup fenv implementation
> 
> Improve feenableexcept performance - avoid an unnecessary FPCR read in case
> the FPCR does not change. Also improve the logic of the return value.
> 
> ChangeLog:
> 2014-10-23  Wilco Dijkstra  <wdijkstr@arm.com>
> 
> 	* sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept):
> 	Optimize to avoid an unnecessary FPCR read.
> 
> ---
>  sysdeps/aarch64/fpu/feenablxcpt.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
> index 763248f..dfb4120 100644
> --- a/sysdeps/aarch64/fpu/feenablxcpt.c
> +++ b/sysdeps/aarch64/fpu/feenablxcpt.c
> @@ -24,24 +24,22 @@ feenableexcept (int excepts)
>  {
>    fpu_control_t fpcr;
>    fpu_control_t fpcr_new;
> +  fpu_control_t updated_fpcr;
> 
>    _FPU_GETCW (fpcr);
>    excepts &= FE_ALL_EXCEPT;
>    fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT);
> 
>    if (fpcr != fpcr_new)
> -    _FPU_SETCW (fpcr_new);
> -
> -  /* Trapping exceptions are optional in AArch64 the relevant enable
> -     bits in FPCR are RES0 hence the absence of support can be
> -     detected by reading back the FPCR and comparing with the required
> -     value.  */
> -  if (excepts)
>      {
> -      fpu_control_t updated_fpcr;
> +      _FPU_SETCW (fpcr_new);
> 
> +      /* Trapping exceptions are optional in AArch64; the relevant enable
> +	 bits in FPCR are RES0 hence the absence of support can be detected
> +	 by reading back the FPCR and comparing with the required value.  */
>        _FPU_GETCW (updated_fpcr);
> -      if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
> +
> +      if (fpcr_new & ~updated_fpcr)
>  	return -1;
>      }
> 
> --
> 1.9.1