[PATCH 2/N, MPX, x86_64] Intel MPX support in glibc for x86_64

[H.J. Lu]

On Tue, Mar 18, 2014 at 7:22 AM, Zamyatin, Igor <igor.zamyatin@intel.com> wrote:
> Hi All!
>
> Attached patch continues (see the beginning here - http://sourceware.org/ml/libc-alpha/2014-03/msg00491.html) adding support for Intel MPX in Glibc for x86_64. Current change performs storing and restoring of bound registers before and after _dl_profile_fixup call.
>
> Is it ok to install?
>
> 2014-03-18  Igor Zamyatin  <igor.zamyatin@intel.com>
>
>         * sysdeps/x86_64/bits/link.h (La_x86_64_regs): Add lr_bnd.
>         (La_x86_64_retval): Add lrv_bnd0 and lrv_bnd1.
>         * sysdeps/x86_64/dl-trampoline.S (_dl_runtime_profile): Add preserving
>         of the Intel MPX bound registers before call of _dl_profile_fixup.
>         * sysdeps/x86_64/dl-trampoline.h: Add restoring of the Intel MPX bound
>         registers after call of _dl_profile_fixup.

I checked in the first patch.  Please rebase this one.
A couple comments:

1.  Please test both MPX and non-MPX binuitils.
2.
+# ifndef __ILP32__
+#  ifdef HAVE_MPX_SUPPORT
+ bndmov %bnd0,   (LR_BND_OFFSET)(%rsp)  # Preserve bound
+ bndmov %bnd1, (LR_BND_OFFSET +   BND_SIZE)(%rsp)  # registers. Nops if
+ bndmov %bnd2, (LR_BND_OFFSET + BND_SIZE*2)(%rsp)  # MPX not available
+ bndmov %bnd3, (LR_BND_OFFSET + BND_SIZE*3)(%rsp)  # or disabled.
+#  else
+ byte 0x66,0x0f,0x1b,0x84,0x24,0xc0,0x02,0x00,0x00
+ byte 0x66,0x0f,0x1b,0x8c,0x24,0xd0,0x02,0x00,0x00
+ byte 0x66,0x0f,0x1b,0x84,0x24,0xe0,0x02,0x00,0x00
+ byte 0x66,0x0f,0x1b,0x8c,0x24,0xf0,0x02,0x00,0x00
^^^^^^^^^  This should be .byte.
+#  endif
+# endif
3.
byte 0x66,0x0f,0x1b,0x84,0x24,0xc0,0x02,0x00,0x00
                                              ^^^^^^^^^^^^^^^^^^^^^^^ This
hardcods the offset.  Please add

#if LR_BND_OFFSET != xxxx
#  error LR_BND_OFFSET is not xxx
#endif


-- 
H.J.