[PATCH] Don't use SSE4_2 instructions on Intel Silvermont Micro Architecture.

[Carlos O'Donell]

On 06/19/2013 03:44 PM, Dmitrieva Liubov wrote:
> My patch is ready. Ok to commit?
> 
> Change Log.
> 
> 2013-06-19  Liubov Dmitrieva  <liubov.dmitrieva@intel.com>
> 
> * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
> Set bit_Slow_SSE4_2 for Intel Silvermont architecture.
> Set bit_Prefer_PMINUB_for_stringop for Intel Silvermont.
> * sysdeps/x86_64/multiarch/init-arch.h: Define
> bit_Slow_SSE4_2 and index_Slow_SSE4_2.
> Define index_Prefer_PMINUB_for_stringop which was undefined.
> * sysdeps/x86_64/multiarch/strchr.S: Use SSE2 version if
> bit_Slow_SSE4_2 is on.
> * sysdeps/x86_64/multiarch/strrchr.S: Use SSE2 version if
> bit_Slow_SSE4_2 is on.
> * sysdeps/x86_64/multiarch/strcmp.S: Use SSSE3 or SSE2 version if
> bit_Slow_SSE4_2 is on.

We have string operations in the glibc microbenchmark.

Can you show that this patch makes a performance improvement on Silvermont?

What are the string op numbers before and after your patch?

Cheers,
Carlos.