[Patch] Memory fencing fixes

[Joseph S. Myers]

On Mon, 25 Feb 2013, Jeff Law wrote:

> > > --- a/ports/sysdeps/arm/bits/atomic.h
> > > +++ b/ports/sysdeps/arm/bits/atomic.h
> > > @@ -42,6 +42,7 @@ void __arm_link_error (void);
> > >   # define atomic_full_barrier() __sync_synchronize ()
> > >   #else
> > >   # define atomic_full_barrier() __arm_assisted_full_barrier ()
> > > +# define atomic_asm_full_barrier() __arm_asm_assisted_full_barrier ()
> > >   #endif
> > 
> > This is only defining atomic_asm_full_barrier in one case of this
> > conditional - don't you need a definition in the
> > __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 case as well?  It looks like you're
> > using this macro unconditionally.
> I thought I took this from Carlos's or your work.  What's the right code to
> use when GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 is defined?  just
> __sync_synchronize?

That's a builtin and as I understand it you want something that can be 
used inside an inline asm here, i.e. a string of assembler instructions.  
The barrier GCC uses for TARGET_HAVE_DMB is "dmb\tsy", otherwise 
"mcr\tp15, 0, r0, c7, c10, 5" for TARGET_HAVE_DMB_MCR.  So you could put 
in appropriate conditionals depending on whether v7 or above.  With GCC 
4.8 you have the __ARM_ARCH macro that can be used in such conditionals, 
but before that you just have the __ARM_ARCH_*__ macros for each 
architecture version.

-- 
Joseph S. Myers
joseph@codesourcery.com