benchmark for atomic.

[Ondřej Bílka]

On Mon, Dec 16, 2013 at 10:23:34PM +0100, Ondřej Bílka wrote:
> > 
> > > Second problem is that fastbins are per-arena not per-thread which
> > > forces us to use atomic operations. These are expensive (typicaly more than 50 cycles).
> > 
> > Especially on x86, atomic operations that *hit in the cache* have become
> > very fast compared to their costs in the past.  I don't have current
> > numbers, but I believe the 50 cycle number is too high; I vaguely
> > remember 10-20.
> 
> A simple benchmark could check a real cost. A problem is that while for core2
> and i7 cost of CAS is around 20 cycles for bulldozer its still 50 cycles.
> 
> Even with these a malloc+free pair contains 5 atomic instructions on
> fastbin path which gives 100 cycle penalty (malloc: lock, get item from bin, unlock,
> free: set bit that fastbins are in use, put item to bin) 
> 
A benchmark for performance of CAS is here.
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#include <stdint.h>
#include <stdio.h>
#include <pthread.h>
static uint64_t  __attribute__((noinline)) rdtsc(void)
{
  uint32_t lo, hi;
  __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
  return (uint64_t)hi << 32 | lo;
}

uint64_t x;
char y[100];

void fn(void *x)
{
  int i = 0;
  while (1)
    {
      y[(i%100)] = 42;
      i++;
    }
}

int main()
{
  x = 0;
  int i;
  int times=10000000;
  pthread_t thread;
#ifdef THREAD
 pthread_create (&thread, NULL, (void *) &fn, NULL);
#endif
  uint64_t start = rdtsc();
  for (i=0;i<times;i++)
   {
     __sync_bool_compare_and_swap (&x,i,i+1);
   }
  uint64_t end = rdtsc();
  printf ("%lli\n", (end-start)/times);
}