[PATCH] Fix underflow reporting and tie up loose ends in sparc soft-fp.

[David Miller]

From: Richard Henderson <rth@twiddle.net>
Date: Tue, 29 May 2012 10:44:31 -0700

> The thing that the former code does that the later does not is
> raise SIGFPE in the event that the exception is not masked.

The CPU will take the FPU exception when you write the bits into the
FSR if any bits found in CEXC are also set in TEM.

I've tested this.