[PATCH] PPC remove use of phased-out mftb instructions

Steven Munroe munroesj@linux.vnet.ibm.com
Thu Apr 10 17:28:00 GMT 2008


On Thu, 2008-04-10 at 09:06 +1000, Paul Mackerras wrote:
> Steven Munroe writes:
> 
> > the POWER ISA-2.03 has marked the move from time base instruction
> > "Phased-out" in favor of the equivalent move from SPR 268.
> > 
> > To continue support for processors I conditioned this on the _ARCH_PWR4.
> > which defined for --with-cpu= or CFLAGS='-mcpu=' power4 and higher.
> 
> I am pretty sure there were never any PowerPC processor
> implementations that implemented mftb, that implemented it any
> differently from mfspr.  I recall checking at least the 603, 604,
> 7400, 7410 and 7455, and IIRC they all executed mfspr rn,268 as
> mftb rn.
> 
they execute the same function but have different opcodes:

mftb is	31,371, tbr = 268,269
mfspr is 31,339, spr = 268,269

The current glibc hp-timing support is definitely running the 31,371
opcode which hardware wants to remove mftb with ISA V2.06.

The ISA 2.05 explicitly states that all V 2.01+ processors currently
support both, but older processors (including POWER3 and 601) do not
support the mfspr 268.

POWER4 is the first ISA 2.01 64-bit implementation and it was simple to
use _ARCH_PWR4 to condition the switch .

For 32-bit it is more complicated as 601 did not support the PowerPC
timebase at all. As a result general powerpc32 did not have hp-timing
support. Also I simply don't know the history of Motorola and Freescale
chips and no one from that community has come forward to add --with-cpu=
support for those chips.

So it was simplest and safest to copy the powerpc64 hp-timing supports
from powerpc64 to powerpc32/power4. This covers 32-bit mode for the
processors I know and does not harm otherwise.

> So I don't think it's necessary to condition it.  I could repeat the
> tests and do them across a broader range of processors if that would
> be helpful.
> 
> Paul.



More information about the Libc-alpha mailing list