[PATCH] PowerPC: Extend fpu fenv operations to operate on 64-bit FPSCR

[Ryan S. Arnold]

On Tue, 2007-10-30 at 17:18 -0500, Ryan S. Arnold wrote:

> Hi Ulrich,
> 
> This error is due to an overly simplistic test-case expectation on my
> part but the underlying new FPSCR code is still sound.  I found the same
> issue in my new test-powerpc-fenv testcase.
> 
> On the pre-POWER6 series of hardware (POWER5, et al) the high order word
> of the FPSCR 0:31 is 'undefined' after the mffs instruction.  This value
> 0xfff80000 just happens to be what populates the high-order word before
> the _FPU_SETCW.
> 
> Currently fegetenv() will exhibit an undefined high-order word in the
> fenv_t.  Likewise we'll be leaving the high-order 32-bits 'undefined' in
> the unsigned long long int fpu_control_t.  
> 
> I originally tested this on a Power6 with and without -mcpu=power6
> specified where the high-order word of the FPSCR register isn't touched
> by the two operand mtfsf instruction.  I've learned my lesson and will
> make sure to test on completely different hardware next time.
> 
> I'll regenerate and verify a clean make check on different classes of
> POWER hardware.

Okay, I regenerated the patch.  I was able to conditionally exclude the
high order word test on non-POWER6 hardware per the explanation above.

I ran make check successfully across these test cases on POWER5 and
POWER6.

Ryan S. Arnold
IBM Linux Technology Center
Linux Toolchain Development
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