[PATCH] PPC optimize memset for POWER6

[Steven Munroe]

The current ./power6/memset.S implementations are based on the power5
design which hits a number of power6 hazards includes instruction cache
alignment, branch miss-predicts, ans store queue overrun. The attached
patch is a major rewrite of the ./powerpc32/power6/memset.S and
./powerpc64/power6/memset.S to address these issues for lengths 32-bytes
and larger. These implementations uses agressive loop unrolling to favor
branch fall-through (not taken) and avoid I cache refetch due to branch
miss-predict.

the performance improvement over this interval range from 40% to 200%

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