New x86-64 memcpy
Jakub Jelinek
jakub@redhat.com
Tue Feb 27 22:18:00 GMT 2007
On Fri, Feb 16, 2007 at 05:38:46PM -0600, Menezes, Evandro wrote:
> I implemented a new version of memcpy for x86-64 that provides an overall
> performance improvement over the current one on both AMD and Intel
> processors.
>
> It has several algorithms tuned for specific block size ranges,
> considering the sizes of the cache subsystems. For instance, making use
> of repeated string instructions, software prefetching and streaming
> stores.
>
> As it uses several algorithms depending on the block size, the code is
> fairly long. But given that ld.so doesn't really need as many algorithms,
> at build-time a specialized version for ld.so has only a handful of worthy
> algorithms.
>
> In addition to the source-code patches, I also attached the resulting data
> obtained on a 2.4GHz Athlon64 with DDR2-800 RAM and on a 3GHz Core2 with
> DDR2-533. The file memcpy-opteron-old.txt has the original output of
> string/test-memcpy on the Athlon64 system and the file
> memcpy-opteron-new.txt the output using the new routine. The files
> memcpy-core2-old.txt and memcpy-core2-new.txt contain the same results but
> on the Core2 system.
I see a few issues:
1) as the l1/l2 cache sizes and prefetchw flag are only used in libc.so
version, there is no point to have those vars (why were they 8 byte rather
than 4 byte btw?) in _rtld_global, they can very well be hidden inside
of libc.so, therefore they can be accessed like:
movl _x86_64_l1_cache_size_half(%rip), %r8d
which is certainly faster than loading its address from GOT and then
using second memory load read the actual value. The values can be
initialized in a static routine with constructor attribute.
2) even for Intel CPUs it is possible to determine L1 data cache size
and glibc's sysconf (_SC_LEVEL1_DCACHE_SIZE) already knows how to do it
3) the function didn't have cfi directives, eventhough it changes %rsp
and saves/restores call saved registers
4) various formatting issues (spaces instead of tabs etc.)
5) glibc i?86/x86_64 assembly style uses explicit instruction suffixes
So, attached are the two patches combined with the above things changed.
Initially I thought cacheinfo.c could just call
__sysconf (_SC_LEVEL1_DCACHE_SIZE) and __sysconf (_SC_LEVEL2_CACHE_SIZE),
unfortunately that doesn't work because the test ld.so (the one to determine
which objects are needed to compile from libc_pic.a as rtld-*.os)
doesn't link then - the real sysconf just brings with it too much
from libc_pic.a. Perhaps even better would be to unify the cacheinfo
detection between i386 and x86_64 (basically have one common
cacheinfo.h with most of the routines, but using cpuid inline routine)
and then separate i386 and x86_64 cacheinfo.c including it and defining
its own version of cpuid inline (on x86_64 we don't need to dance around
%ebx), i386 cacheinfo.c would include detection whether cpuid insn
can be used at all and x86_64 cacheinfo.c would include these new
_x86_64_* variables and constructor.
BTW, why do you use push/pop instead of just saving/restoring the values
from red zone? That would mean at least simpler unwind info.
Also, for mempcpy, IMHO it is a bad idea to compute result value early,
I believe in all code paths the right return value is available in %rdi
register, so the pushq/popq %rax would be unneeded for mempcpy and instead
before each rep; retq you'd add #if MEMPCPY_P movq %rdi, %rax #endif.
Looking at test-memcpy numbers (which I admit is certainly not a good
benchmark), I don't see very visible win on quadcore Core2 though:
$ ~/timing elf/ld.so --library-path vanilla/ string/test-memcpy --direct > /dev/null
Strip out best and worst realtime result
minimum: 0.858424000 sec real / 0.000017988 sec CPU
maximum: 0.885605000 sec real / 0.000041098 sec CPU
average: 0.862428714 sec real / 0.000019401 sec CPU
stdev : 0.002703822 sec real / 0.000001518 sec CPU
$ ~/timing elf/ld.so --library-path . string/test-memcpy --direct > /dev/null
Strip out best and worst realtime result
minimum: 0.857600000 sec real / 0.000017456 sec CPU
maximum: 1.162678000 sec real / 0.000036033 sec CPU
average: 0.859858000 sec real / 0.000019178 sec CPU
stdev : 0.001414669 sec real / 0.000001500 sec CPU
$ ~/timing elf/ld.so --library-path vanilla/ string/test-memcpy --direct > /dev/null
Strip out best and worst realtime result
minimum: 0.858311000 sec real / 0.000017796 sec CPU
maximum: 0.905352000 sec real / 0.000038400 sec CPU
average: 0.861902142 sec real / 0.000019158 sec CPU
stdev : 0.002512279 sec real / 0.000000852 sec CPU
$ ~/timing elf/ld.so --library-path . string/test-memcpy --direct > /dev/null
Strip out best and worst realtime result
minimum: 0.857419000 sec real / 0.000018074 sec CPU
maximum: 0.870351000 sec real / 0.000032102 sec CPU
average: 0.861215571 sec real / 0.000019397 sec CPU
stdev : 0.002651920 sec real / 0.000001001 sec CPU
$ ~/timing elf/ld.so --library-path vanilla/ string/test-memcpy --direct > /dev/null
Strip out best and worst realtime result
minimum: 0.858271000 sec real / 0.000017894 sec CPU
maximum: 0.866028000 sec real / 0.000038928 sec CPU
average: 0.862063750 sec real / 0.000019215 sec CPU
stdev : 0.002647184 sec real / 0.000000988 sec CPU
$ ~/timing elf/ld.so --library-path . string/test-memcpy --direct > /dev/null
Strip out best and worst realtime result
minimum: 0.857654000 sec real / 0.000018043 sec CPU
maximum: 1.393263000 sec real / 0.000036258 sec CPU
average: 0.860786428 sec real / 0.000019350 sec CPU
stdev : 0.002447096 sec real / 0.000000892 sec CPU
I will certainly retry tonight on Athlon64 X2 when I get
physically to it. In any case e.g. SPEC numbers would
be interesting too.
Jakub
-------------- next part --------------
--- libc/sysdeps/x86_64/cacheinfo.c.jj 2007-02-27 13:13:39.000000000 +0100
+++ libc/sysdeps/x86_64/cacheinfo.c 2007-02-27 15:43:42.000000000 +0100
@@ -0,0 +1,406 @@
+/* x86_64 cache info.
+ Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+static const struct intel_02_cache_info
+{
+ unsigned int idx;
+ int name;
+ long int size;
+ long int assoc;
+ long int linesize;
+} intel_02_known[] =
+ {
+ { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
+ { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
+ { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
+ { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
+ { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
+ { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
+ { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
+ { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
+ { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
+ { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
+ { 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
+ { 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
+ { 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
+ { 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
+ { 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
+ { 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
+ { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
+ { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
+ { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
+ { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
+ { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
+ { 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
+ { 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
+ { 0x49, _SC_LEVEL2_CACHE_SIZE, 4194304, 16, 64 },
+ { 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
+ { 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
+ { 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
+ { 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
+ { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
+ { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
+ { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
+ { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
+ { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
+ { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
+ { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
+ { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
+ { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
+ { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
+ { 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
+ { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
+ { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
+ { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
+ { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
+ { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
+ { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
+ };
+#define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
+
+
+static int
+intel_02_known_compare (const void *p1, const void *p2)
+{
+ const struct intel_02_cache_info *i1;
+ const struct intel_02_cache_info *i2;
+
+ i1 = (const struct intel_02_cache_info *) p1;
+ i2 = (const struct intel_02_cache_info *) p2;
+
+ if (i1->idx == i2->idx)
+ return 0;
+
+ return i1->idx < i2->idx ? -1 : 1;
+}
+
+
+static long int
+__attribute__ ((noinline))
+intel_check_word (int name, unsigned int value, bool *has_level_2,
+ bool *no_level_2_or_3)
+{
+ if ((value & 0x80000000) != 0)
+ /* The register value is reserved. */
+ return 0;
+
+ /* Fold the name. The _SC_ constants are always in the order SIZE,
+ ASSOC, LINESIZE. */
+ int folded_name = (_SC_LEVEL1_ICACHE_SIZE
+ + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
+
+ while (value != 0)
+ {
+ unsigned int byte = value & 0xff;
+
+ if (byte == 0x40)
+ {
+ *no_level_2_or_3 = true;
+
+ if (folded_name == _SC_LEVEL3_CACHE_SIZE)
+ /* No need to look further. */
+ break;
+ }
+ else
+ {
+ if (byte == 0x49 && folded_name == _SC_LEVEL3_CACHE_SIZE)
+ {
+ /* Intel reused this value. For family 15, model 6 it
+ specifies the 3rd level cache. Otherwise the 2nd
+ level cache. */
+ unsigned int eax;
+ unsigned int ebx;
+ unsigned int ecx;
+ unsigned int edx;
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (1));
+
+ unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
+ unsigned int model = ((((eax >>16) & 0xf) << 4)
+ + ((eax >> 4) & 0xf));
+ if (family == 15 && model == 6)
+ {
+ /* The level 3 cache is encoded for this model like
+ the level 2 cache is for other models. Pretend
+ the caller asked for the level 2 cache. */
+ name = (_SC_LEVEL2_CACHE_SIZE
+ + (name - _SC_LEVEL3_CACHE_SIZE));
+ folded_name = _SC_LEVEL3_CACHE_SIZE;
+ }
+ }
+
+ struct intel_02_cache_info *found;
+ struct intel_02_cache_info search;
+
+ search.idx = byte;
+ found = bsearch (&search, intel_02_known, nintel_02_known,
+ sizeof (intel_02_known[0]), intel_02_known_compare);
+ if (found != NULL)
+ {
+ if (found->name == folded_name)
+ {
+ unsigned int offset = name - folded_name;
+
+ if (offset == 0)
+ /* Cache size. */
+ return found->size;
+ if (offset == 1)
+ return found->assoc;
+
+ assert (offset == 2);
+ return found->linesize;
+ }
+
+ if (found->name == _SC_LEVEL2_CACHE_SIZE)
+ *has_level_2 = true;
+ }
+ }
+
+ /* Next byte for the next round. */
+ value >>= 8;
+ }
+
+ /* Nothing found. */
+ return 0;
+}
+
+
+static long int __attribute__ ((noinline))
+handle_intel (int name, unsigned int maxidx)
+{
+ assert (maxidx >= 2);
+
+ /* OK, we can use the CPUID instruction to get all info about the
+ caches. */
+ unsigned int cnt = 0;
+ unsigned int max = 1;
+ long int result = 0;
+ bool no_level_2_or_3 = false;
+ bool has_level_2 = false;
+ while (cnt++ < max)
+ {
+ unsigned int eax;
+ unsigned int ebx;
+ unsigned int ecx;
+ unsigned int edx;
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (2));
+
+ /* The low byte of EAX in the first round contain the number of
+ rounds we have to make. At least one, the one we are already
+ doing. */
+ if (cnt == 1)
+ {
+ max = eax & 0xff;
+ eax &= 0xffffff00;
+ }
+
+ /* Process the individual registers' value. */
+ result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
+ if (result != 0)
+ return result;
+
+ result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
+ if (result != 0)
+ return result;
+
+ result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
+ if (result != 0)
+ return result;
+
+ result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
+ if (result != 0)
+ return result;
+ }
+
+ if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
+ && no_level_2_or_3)
+ return -1;
+
+ return 0;
+}
+
+
+static long int __attribute__ ((noinline))
+handle_amd (int name)
+{
+ unsigned int eax;
+ unsigned int ebx;
+ unsigned int ecx;
+ unsigned int edx;
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (0x80000000));
+
+ if (name >= _SC_LEVEL3_CACHE_SIZE)
+ return 0;
+
+ unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
+ if (eax < fn)
+ return 0;
+
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (fn));
+
+ if (name < _SC_LEVEL1_DCACHE_SIZE)
+ {
+ name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
+ ecx = edx;
+ }
+
+ switch (name)
+ {
+ case _SC_LEVEL1_DCACHE_SIZE:
+ return (ecx >> 14) & 0x3fc00;
+ case _SC_LEVEL1_DCACHE_ASSOC:
+ ecx >>= 16;
+ if ((ecx & 0xff) == 0xff)
+ /* Fully associative. */
+ return (ecx << 2) & 0x3fc00;
+ return ecx & 0xff;
+ case _SC_LEVEL1_DCACHE_LINESIZE:
+ return ecx & 0xff;
+ case _SC_LEVEL2_CACHE_SIZE:
+ return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
+ case _SC_LEVEL2_CACHE_ASSOC:
+ ecx >>= 12;
+ switch (ecx & 0xf)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 4:
+ return ecx & 0xf;
+ case 6:
+ return 8;
+ case 8:
+ return 16;
+ case 0xf:
+ return (ecx << 6) & 0x3fffc00;
+ default:
+ return 0;
+ }
+ case _SC_LEVEL2_CACHE_LINESIZE:
+ return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
+ default:
+ assert (! "cannot happen");
+ }
+ return -1;
+}
+
+
+/* Get the value of the system variable NAME. */
+long int
+attribute_hidden
+__cache_sysconf (int name)
+{
+ /* Find out what brand of processor. */
+ unsigned int eax;
+ unsigned int ebx;
+ unsigned int ecx;
+ unsigned int edx;
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (0));
+
+ /* This spells out "GenuineIntel". */
+ if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
+ return handle_intel (name, eax);
+
+ /* This spells out "AuthenticAMD". */
+ if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
+ return handle_amd (name);
+
+ // XXX Fill in more vendors.
+
+ /* CPU not known, we have no information. */
+ return 0;
+}
+
+
+/* L1 cache size for use in memory and string routines. */
+int _x86_64_l1_cache_size = 32 * 1024;
+int _x86_64_l1_cache_size_half = 32 * 1024 / 2;
+/* L2 cache size for use in memory and string routines. */
+int _x86_64_l2_cache_size = 1024 * 1024;
+int _x86_64_l2_cache_size_half = 1024 * 1024 / 2;
+int _x86_64_use_prefetchw = 0;
+
+
+static void __attribute__((constructor))
+init_cacheinfo (void)
+{
+ /* Find out what brand of processor. */
+ unsigned int eax;
+ unsigned int ebx;
+ unsigned int ecx;
+ unsigned int edx;
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (0));
+
+ long int l1 = -1;
+ long int l2 = -1;
+
+ /* This spells out "GenuineIntel". */
+ if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
+ {
+ l1 = handle_intel (_SC_LEVEL1_DCACHE_SIZE, eax);
+ l2 = handle_intel (_SC_LEVEL2_CACHE_SIZE, eax);
+ }
+
+ /* This spells out "AuthenticAMD". */
+ else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
+ {
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (0x80000000));
+ if (eax >= 0x80000001)
+ {
+ asm volatile ("cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "0" (0x80000001));
+ /* PREFETCHW || 3DNow! */
+ if ((ecx & 0x100) || (edx & 0x80000000))
+ _x86_64_use_prefetchw = -1;
+ }
+ l1 = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
+ l2 = handle_amd (_SC_LEVEL2_CACHE_SIZE);
+ }
+
+ if (l1 > 0)
+ {
+ _x86_64_l1_cache_size = l1;
+ _x86_64_l1_cache_size_half = l1 / 2;
+ }
+
+ if (l2 > 0)
+ {
+ _x86_64_l2_cache_size = l2;
+ _x86_64_l2_cache_size_half = l2 / 2;
+ }
+}
--- libc/sysdeps/x86_64/Makefile.jj 2004-08-16 08:46:14.000000000 +0200
+++ libc/sysdeps/x86_64/Makefile 2007-02-27 14:22:44.000000000 +0100
@@ -9,3 +9,7 @@ endif
ifeq ($(subdir),gmon)
sysdep_routines += _mcount
endif
+
+ifeq ($(subdir),string)
+sysdep_routines += cacheinfo
+endif
--- libc/sysdeps/x86_64/memcpy.S.jj 2006-10-31 23:08:34.000000000 +0100
+++ libc/sysdeps/x86_64/memcpy.S 2007-02-27 14:58:54.000000000 +0100
@@ -1,7 +1,8 @@
-/* Highly optimized version for x86-64.
- Copyright (C) 1997, 2000, 2002, 2003, 2004 Free Software Foundation, Inc.
+/* Optimized memcpy for x86-64.
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Contributed by Evandro Menezes <evandro.menezes@amd.com>, 2007.
+
This file is part of the GNU C Library.
- Based on i586 version contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -16,12 +17,11 @@
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307 USA. */
+ 02111-1307 USA.
+*/
#include <sysdep.h>
#include "asm-syntax.h"
-#include "bp-sym.h"
-#include "bp-asm.h"
/* BEWARE: `#ifdef memcpy' means that memcpy is redefined as `mempcpy',
and the return value is the byte after the last one copied in
@@ -35,67 +35,500 @@ ENTRY (__memcpy_chk)
jb HIDDEN_JUMPTARGET (__chk_fail)
END (__memcpy_chk)
#endif
-ENTRY (BP_SYM (memcpy))
- /* Cutoff for the big loop is a size of 32 bytes since otherwise
- the loop will never be entered. */
+
+ENTRY(memcpy) /* (void *, const void*, size_t) */
+
+/* Handle tiny blocks. */
+
+L(1try): /* up to 32B */
cmpq $32, %rdx
- movq %rdx, %rcx
-#if !MEMPCPY_P
- movq %rdi, %r10 /* Save value. */
+#if MEMPCPY_P
+ leaq (%rdi, %rdx), %rax
+#else
+ movq %rdi, %rax
#endif
+ jae L(1after)
- /* We need this in any case. */
- cld
+L(1): testb $1, %dl /* 1-byte once */
+ jz L(1a)
- jbe 1f
+ movzbl (%rsi), %ecx
+ movb %cl, (%rdi)
- /* Align destination. */
- movq %rdi, %rax
- negq %rax
- andq $7, %rax
- subq %rax, %rcx
- xchgq %rax, %rcx
+ incq %rsi
+ incq %rdi
+
+L(1a): testb $2, %dl /* 2-byte once */
+ jz L(1b)
+
+ movzwl (%rsi), %ecx
+ movw %cx, (%rdi)
+
+ addq $2, %rsi
+ addq $2, %rdi
+
+L(1b): testb $4, %dl /* 4-byte once */
+ jz L(1c)
+
+ movl (%rsi), %ecx
+ movl %ecx, (%rdi)
+
+ addq $4, %rsi
+ addq $4, %rdi
+
+L(1c): testb $8, %dl /* 8-byte once */
+ jz L(1d)
+
+ movq (%rsi), %rcx
+ movq %rcx, (%rdi)
+
+ addq $8, %rsi
+ addq $8, %rdi
+
+L(1d): andl $0xf0, %edx /* 16-byte loop */
+ jz L(exit)
+
+ .p2align 4
+L(1loop):
+ movq (%rsi), %rcx
+ movq 8(%rsi), %r8
+ movq %rcx, (%rdi)
+ movq %r8, 8(%rdi)
+
+ subl $16, %edx
+
+ leaq 16(%rsi), %rsi
+ leaq 16(%rdi), %rdi
+
+ jnz L(1loop)
+
+ .p2align 4,, 4
+
+L(exit): /* exit */
+ rep
+ retq
+
+ .p2align 4
+
+L(1after):
+ pushq %rax
+ cfi_adjust_cfa_offset(8)
+
+/* Align to the natural word size. */
- rep; movsb
+L(aligntry):
+ movl %edi, %ecx /* align by destination */
- movq %rax, %rcx
- subq $32, %rcx
- js 2f
+ andl $7, %ecx
+ jz L(alignafter) /* already aligned */
+
+L(align): /* align */
+ leaq -8(%rcx, %rdx), %rdx /* calculate remaining bytes */
+ subl $8, %ecx
+
+ .p2align 4
+
+L(alignloop): /* 1-byte alignment loop */
+ movzbl (%rsi), %eax
+ movb %al, (%rdi)
+
+ incl %ecx
+
+ leaq 1(%rsi), %rsi
+ leaq 1(%rdi), %rdi
+
+ jnz L(alignloop)
+
+ .p2align 4
+
+L(alignafter):
+
+/* Loop to handle mid-sized blocks. */
+
+L(32try): /* up to 1KB */
+ cmpq $1024, %rdx
+ ja L(32after)
+
+L(32): /* 32-byte loop */
+ movl %edx, %ecx
+ shrl $5, %ecx
+ jz L(32skip)
.p2align 4
-3:
- /* Now correct the loop counter. Please note that in the following
- code the flags are not changed anymore. */
- subq $32, %rcx
+L(32loop):
+ decl %ecx
movq (%rsi), %rax
- movq 8(%rsi), %rdx
- movq 16(%rsi), %r8
- movq 24(%rsi), %r9
+ movq 8(%rsi), %r8
+ movq 16(%rsi), %r9
+ movq 24(%rsi), %r10
+
movq %rax, (%rdi)
- movq %rdx, 8(%rdi)
- movq %r8, 16(%rdi)
- movq %r9, 24(%rdi)
+ movq %r8, 8(%rdi)
+ movq %r9, 16(%rdi)
+ movq %r10, 24(%rdi)
leaq 32(%rsi), %rsi
leaq 32(%rdi), %rdi
- jns 3b
+ jz L(32skip) /* help out smaller blocks */
- /* Correct extra loop counter modification. */
-2: addq $32, %rcx
-1: rep; movsb
+ decl %ecx
-#if MEMPCPY_P
- movq %rdi, %rax /* Set return value. */
+ movq (%rsi), %rax
+ movq 8(%rsi), %r8
+ movq 16(%rsi), %r9
+ movq 24(%rsi), %r10
+
+ movq %rax, (%rdi)
+ movq %r8, 8(%rdi)
+ movq %r9, 16(%rdi)
+ movq %r10, 24(%rdi)
+
+ leaq 32(%rsi), %rsi
+ leaq 32(%rdi), %rdi
+
+ jnz L(32loop)
+
+ .p2align 4
+
+L(32skip):
+ andl $31, %edx /* check for left overs */
+ popq %rax
+ cfi_adjust_cfa_offset(-8)
+ jnz L(1)
+
+ rep /* exit */
+ retq
+
+ .p2align 4
+
+L(32after):
+ cfi_adjust_cfa_offset(8)
+
+/* In order to minimize code-size in RTLD, algorithms specific for
+ larger blocks are excluded when building for RTLD. */
+
+/* Handle large blocks smaller than 1/2 L1. */
+
+L(fasttry): /* first 1/2 L1 */
+#ifndef NOT_IN_libc /* only up to this algorithm outside of libc.so */
+ movl _x86_64_l1_cache_size_half(%rip), %r11d
+ cmpq %rdx, %r11 /* calculate the smaller of */
+ cmovaq %rdx, %r11 /* remaining bytes and 1/2 L1 */
+#endif
+
+L(fast): /* good ol' MOVS */
+#ifndef NOT_IN_libc
+ movq %r11, %rcx
+ andq $-8, %r11
#else
- movq %r10, %rax /* Set return value. */
-
+ movq %rdx, %rcx
+#endif
+ shrq $3, %rcx
+ jz L(fastskip)
+
+ rep
+ movsq
+
+L(fastskip):
+#ifndef NOT_IN_libc
+ subq %r11, %rdx /* check for more */
+ testq $-8, %rdx
+ jnz L(fastafter)
#endif
- ret
-END (BP_SYM (memcpy))
+ andl $7, %edx /* check for left overs */
+ popq %rax
+ cfi_adjust_cfa_offset(-8)
+ jnz L(1)
+
+ rep /* exit */
+ retq
+
+#ifndef NOT_IN_libc /* none of the algorithms below outside of libc.so */
+
+ .p2align 4
+
+L(fastafter):
+ cfi_adjust_cfa_offset(8)
+
+/* Handle large blocks smaller than 1/2 L2. */
+
+L(pretry): /* first 1/2 L2 */
+ movl _x86_64_l2_cache_size_half(%rip), %r8d
+ cmpq %rdx, %r8 /* calculate the lesser of */
+ cmovaq %rdx, %r8 /* remaining bytes and 1/2 L2 */
+
+L(pre): /* 64-byte with prefetching */
+ movq %r8, %rcx
+ andq $-64, %r8
+ shrq $6, %rcx
+ jz L(preskip)
+
+ pushq %r14
+ cfi_adjust_cfa_offset(8)
+ pushq %r13
+ cfi_adjust_cfa_offset(8)
+ pushq %r12
+ cfi_adjust_cfa_offset(8)
+ pushq %rbx
+ cfi_adjust_cfa_offset(8)
+ cfi_rel_offset(%r14, 24)
+ cfi_rel_offset(%r13, 16)
+ cfi_rel_offset(%r12, 8)
+ cfi_rel_offset(%rbx, 0)
+
+ cmpl $0, _x86_64_use_prefetchw(%rip)
+ jz L(preloop) /* check if PREFETCHW OK */
+
+ .p2align 4
+
+/* ... when PREFETCHW is available (less cache-probe traffic in MP systems). */
+
+L(prewloop): /* cache-line in state M */
+ decq %rcx
+
+ movq (%rsi), %rax
+ movq 8(%rsi), %rbx
+ movq 16(%rsi), %r9
+ movq 24(%rsi), %r10
+ movq 32(%rsi), %r11
+ movq 40(%rsi), %r12
+ movq 48(%rsi), %r13
+ movq 56(%rsi), %r14
+
+ prefetcht0 0 + 896(%rsi)
+ prefetcht0 64 + 896(%rsi)
+
+ movq %rax, (%rdi)
+ movq %rbx, 8(%rdi)
+ movq %r9, 16(%rdi)
+ movq %r10, 24(%rdi)
+ movq %r11, 32(%rdi)
+ movq %r12, 40(%rdi)
+ movq %r13, 48(%rdi)
+ movq %r14, 56(%rdi)
+
+ leaq 64(%rsi), %rsi
+ leaq 64(%rdi), %rdi
+
+ jz L(prebail)
+
+ decq %rcx
+
+ movq (%rsi), %rax
+ movq 8(%rsi), %rbx
+ movq 16(%rsi), %r9
+ movq 24(%rsi), %r10
+ movq 32(%rsi), %r11
+ movq 40(%rsi), %r12
+ movq 48(%rsi), %r13
+ movq 56(%rsi), %r14
+
+ movq %rax, (%rdi)
+ movq %rbx, 8(%rdi)
+ movq %r9, 16(%rdi)
+ movq %r10, 24(%rdi)
+ movq %r11, 32(%rdi)
+ movq %r12, 40(%rdi)
+ movq %r13, 48(%rdi)
+ movq %r14, 56(%rdi)
+
+ prefetchw 896 - 64(%rdi)
+ prefetchw 896 - 0(%rdi)
+
+ leaq 64(%rsi), %rsi
+ leaq 64(%rdi), %rdi
+
+ jnz L(prewloop)
+ jmp L(prebail)
+
+ .p2align 4
+
+/* ... when PREFETCHW is not available. */
+
+L(preloop): /* cache-line in state E */
+ decq %rcx
+
+ movq (%rsi), %rax
+ movq 8(%rsi), %rbx
+ movq 16(%rsi), %r9
+ movq 24(%rsi), %r10
+ movq 32(%rsi), %r11
+ movq 40(%rsi), %r12
+ movq 48(%rsi), %r13
+ movq 56(%rsi), %r14
+
+ prefetcht0 896 + 0(%rsi)
+ prefetcht0 896 + 64(%rsi)
+
+ movq %rax, (%rdi)
+ movq %rbx, 8(%rdi)
+ movq %r9, 16(%rdi)
+ movq %r10, 24(%rdi)
+ movq %r11, 32(%rdi)
+ movq %r12, 40(%rdi)
+ movq %r13, 48(%rdi)
+ movq %r14, 56(%rdi)
+
+ leaq 64(%rsi), %rsi
+ leaq 64(%rdi), %rdi
+
+ jz L(prebail)
+
+ decq %rcx
+
+ movq (%rsi), %rax
+ movq 8(%rsi), %rbx
+ movq 16(%rsi), %r9
+ movq 24(%rsi), %r10
+ movq 32(%rsi), %r11
+ movq 40(%rsi), %r12
+ movq 48(%rsi), %r13
+ movq 56(%rsi), %r14
+
+ prefetcht0 896 - 64(%rdi)
+ prefetcht0 896 - 0(%rdi)
+
+ movq %rax, (%rdi)
+ movq %rbx, 8(%rdi)
+ movq %r9, 16(%rdi)
+ movq %r10, 24(%rdi)
+ movq %r11, 32(%rdi)
+ movq %r12, 40(%rdi)
+ movq %r13, 48(%rdi)
+ movq %r14, 56(%rdi)
+
+ leaq 64(%rsi), %rsi
+ leaq 64(%rdi), %rdi
+
+ jnz L(preloop)
+
+L(prebail):
+ popq %rbx
+ cfi_adjust_cfa_offset(-8)
+ cfi_restore(%rbx)
+ popq %r12
+ cfi_adjust_cfa_offset(-8)
+ cfi_restore(%r12)
+ popq %r13
+ cfi_adjust_cfa_offset(-8)
+ cfi_restore(%r13)
+ popq %r14
+ cfi_adjust_cfa_offset(-8)
+ cfi_restore(%r14)
+
+/* .p2align 4 */
+
+L(preskip):
+ subq %r8, %rdx /* check for more */
+ testq $-64, %rdx
+ jnz L(preafter)
+
+ andl $63, %edx /* check for left overs */
+ popq %rax
+ cfi_adjust_cfa_offset(-8)
+ jnz L(1)
+
+ rep /* exit */
+ retq
+
+ .p2align 4
+
+/* Loop to handle huge blocks. */
+
+L(preafter):
+L(NTtry):
+L(NT): movq %rdx, %rcx /* non-temporal 128-byte */
+ shrq $7, %rcx
+ jz L(NTskip)
+
+ pushq %r14
+ cfi_adjust_cfa_offset(8)
+ pushq %r13
+ cfi_adjust_cfa_offset(8)
+ pushq %r12
+ cfi_adjust_cfa_offset(8)
+ cfi_rel_offset(%r14, 16)
+ cfi_rel_offset(%r13, 8)
+ cfi_rel_offset(%r12, 0)
+
+ .p2align 4
+
+L(NTloop):
+ prefetchnta 768(%rsi)
+ prefetchnta 832(%rsi)
+
+ decq %rcx
+
+ movq (%rsi), %rax
+ movq 8(%rsi), %r8
+ movq 16(%rsi), %r9
+ movq 24(%rsi), %r10
+ movq 32(%rsi), %r11
+ movq 40(%rsi), %r12
+ movq 48(%rsi), %r13
+ movq 56(%rsi), %r14
+
+ movnti %rax, (%rdi)
+ movnti %r8, 8(%rdi)
+ movnti %r9, 16(%rdi)
+ movnti %r10, 24(%rdi)
+ movnti %r11, 32(%rdi)
+ movnti %r12, 40(%rdi)
+ movnti %r13, 48(%rdi)
+ movnti %r14, 56(%rdi)
+
+ movq 64(%rsi), %rax
+ movq 72(%rsi), %r8
+ movq 80(%rsi), %r9
+ movq 88(%rsi), %r10
+ movq 96(%rsi), %r11
+ movq 104(%rsi), %r12
+ movq 112(%rsi), %r13
+ movq 120(%rsi), %r14
+
+ movnti %rax, 64(%rdi)
+ movnti %r8, 72(%rdi)
+ movnti %r9, 80(%rdi)
+ movnti %r10, 88(%rdi)
+ movnti %r11, 96(%rdi)
+ movnti %r12, 104(%rdi)
+ movnti %r13, 112(%rdi)
+ movnti %r14, 120(%rdi)
+
+ leaq 128(%rsi), %rsi
+ leaq 128(%rdi), %rdi
+
+ jnz L(NTloop)
+
+ sfence /* serialize memory stores */
+
+ popq %r12
+ cfi_adjust_cfa_offset(-8)
+ cfi_restore(%r12)
+ popq %r13
+ cfi_adjust_cfa_offset(-8)
+ cfi_restore(%r13)
+ popq %r14
+ cfi_adjust_cfa_offset(-8)
+ cfi_restore(%r14)
+
+L(NTskip):
+ andl $127, %edx /* check for left overs */
+ popq %rax
+ cfi_adjust_cfa_offset(-8)
+ jnz L(1)
+
+ rep /* exit */
+ retq
+
+#endif /* !NOT_IN_libc */
+
+END(memcpy)
+
#if !MEMPCPY_P
libc_hidden_builtin_def (memcpy)
#endif
--- libc/sysdeps/unix/sysv/linux/x86_64/sysconf.c.jj 2006-11-10 09:01:47.000000000 +0100
+++ libc/sysdeps/unix/sysv/linux/x86_64/sysconf.c 2007-02-27 15:39:54.000000000 +0100
@@ -1,5 +1,5 @@
/* Get file-specific information about a file. Linux version.
- Copyright (C) 2003, 2004, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -24,328 +24,17 @@
static long int linux_sysconf (int name);
-
-
-static const struct intel_02_cache_info
-{
- unsigned int idx;
- int name;
- long int size;
- long int assoc;
- long int linesize;
-} intel_02_known[] =
- {
- { 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
- { 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
- { 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
- { 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
- { 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
- { 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
- { 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
- { 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
- { 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
- { 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
- { 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
- { 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
- { 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
- { 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
- { 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
- { 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
- { 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
- { 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
- { 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
- { 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
- { 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
- { 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
- { 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
- { 0x49, _SC_LEVEL2_CACHE_SIZE, 4194304, 16, 64 },
- { 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
- { 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
- { 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
- { 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
- { 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
- { 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
- { 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
- { 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
- { 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
- { 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
- { 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
- { 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
- { 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
- { 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
- { 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
- { 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
- { 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
- { 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
- { 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
- { 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
- { 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
- };
-#define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
-
-
-static int
-intel_02_known_compare (const void *p1, const void *p2)
-{
- const struct intel_02_cache_info *i1;
- const struct intel_02_cache_info *i2;
-
- i1 = (const struct intel_02_cache_info *) p1;
- i2 = (const struct intel_02_cache_info *) p2;
-
- if (i1->idx == i2->idx)
- return 0;
-
- return i1->idx < i2->idx ? -1 : 1;
-}
-
-
-static long int
-__attribute__ ((noinline))
-intel_check_word (int name, unsigned int value, bool *has_level_2,
- bool *no_level_2_or_3)
-{
- if ((value & 0x80000000) != 0)
- /* The register value is reserved. */
- return 0;
-
- /* Fold the name. The _SC_ constants are always in the order SIZE,
- ASSOC, LINESIZE. */
- int folded_name = (_SC_LEVEL1_ICACHE_SIZE
- + ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
-
- while (value != 0)
- {
- unsigned int byte = value & 0xff;
-
- if (byte == 0x40)
- {
- *no_level_2_or_3 = true;
-
- if (folded_name == _SC_LEVEL3_CACHE_SIZE)
- /* No need to look further. */
- break;
- }
- else
- {
- if (byte == 0x49 && folded_name == _SC_LEVEL3_CACHE_SIZE)
- {
- /* Intel reused this value. For family 15, model 6 it
- specifies the 3rd level cache. Otherwise the 2nd
- level cache. */
- unsigned int eax;
- unsigned int ebx;
- unsigned int ecx;
- unsigned int edx;
- asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
- : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
- : "0" (1));
-
- unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
- unsigned int model = ((((eax >>16) & 0xf) << 4)
- + ((eax >> 4) & 0xf));
- if (family == 15 && model == 6)
- {
- /* The level 3 cache is encoded for this model like
- the level 2 cache is for other models. Pretend
- the caller asked for the level 2 cache. */
- name = (_SC_LEVEL2_CACHE_SIZE
- + (name - _SC_LEVEL3_CACHE_SIZE));
- folded_name = _SC_LEVEL3_CACHE_SIZE;
- }
- }
-
- struct intel_02_cache_info *found;
- struct intel_02_cache_info search;
-
- search.idx = byte;
- found = bsearch (&search, intel_02_known, nintel_02_known,
- sizeof (intel_02_known[0]), intel_02_known_compare);
- if (found != NULL)
- {
- if (found->name == folded_name)
- {
- unsigned int offset = name - folded_name;
-
- if (offset == 0)
- /* Cache size. */
- return found->size;
- if (offset == 1)
- return found->assoc;
-
- assert (offset == 2);
- return found->linesize;
- }
-
- if (found->name == _SC_LEVEL2_CACHE_SIZE)
- *has_level_2 = true;
- }
- }
-
- /* Next byte for the next round. */
- value >>= 8;
- }
-
- /* Nothing found. */
- return 0;
-}
-
-
-static long int __attribute__ ((noinline))
-handle_intel (int name, unsigned int maxidx)
-{
- assert (maxidx >= 2);
-
- /* OK, we can use the CPUID instruction to get all info about the
- caches. */
- unsigned int cnt = 0;
- unsigned int max = 1;
- long int result = 0;
- bool no_level_2_or_3 = false;
- bool has_level_2 = false;
- while (cnt++ < max)
- {
- unsigned int eax;
- unsigned int ebx;
- unsigned int ecx;
- unsigned int edx;
- asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
- : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
- : "0" (2));
-
- /* The low byte of EAX in the first round contain the number of
- rounds we have to make. At least one, the one we are already
- doing. */
- if (cnt == 1)
- {
- max = eax & 0xff;
- eax &= 0xffffff00;
- }
-
- /* Process the individual registers' value. */
- result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
- if (result != 0)
- return result;
-
- result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
- if (result != 0)
- return result;
-
- result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
- if (result != 0)
- return result;
-
- result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
- if (result != 0)
- return result;
- }
-
- if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
- && no_level_2_or_3)
- return -1;
-
- return 0;
-}
-
-
-static long int __attribute__ ((noinline))
-handle_amd (int name)
-{
- unsigned int eax;
- unsigned int ebx;
- unsigned int ecx;
- unsigned int edx;
- asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
- : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
- : "0" (0x80000000));
-
- if (name >= _SC_LEVEL3_CACHE_SIZE)
- return 0;
-
- unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
- if (eax < fn)
- return 0;
-
- asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
- : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
- : "0" (fn));
-
- if (name < _SC_LEVEL1_DCACHE_SIZE)
- {
- name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
- ecx = edx;
- }
-
- switch (name)
- {
- case _SC_LEVEL1_DCACHE_SIZE:
- return (ecx >> 14) & 0x3fc00;
- case _SC_LEVEL1_DCACHE_ASSOC:
- ecx >>= 16;
- if ((ecx & 0xff) == 0xff)
- /* Fully associative. */
- return (ecx << 2) & 0x3fc00;
- return ecx & 0xff;
- case _SC_LEVEL1_DCACHE_LINESIZE:
- return ecx & 0xff;
- case _SC_LEVEL2_CACHE_SIZE:
- return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
- case _SC_LEVEL2_CACHE_ASSOC:
- ecx >>= 12;
- switch (ecx & 0xf)
- {
- case 0:
- case 1:
- case 2:
- case 4:
- return ecx & 0xf;
- case 6:
- return 8;
- case 8:
- return 16;
- case 0xf:
- return (ecx << 6) & 0x3fffc00;
- default:
- return 0;
- }
- case _SC_LEVEL2_CACHE_LINESIZE:
- return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
- default:
- assert (! "cannot happen");
- }
- return -1;
-}
+extern long int __cache_sysconf (int) attribute_hidden;
/* Get the value of the system variable NAME. */
long int
__sysconf (int name)
{
- /* We only handle the cache information here (for now). */
- if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
- return linux_sysconf (name);
-
- /* Find out what brand of processor. */
- unsigned int eax;
- unsigned int ebx;
- unsigned int ecx;
- unsigned int edx;
- asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
- : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
- : "0" (0));
-
- /* This spells out "GenuineIntel". */
- if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
- return handle_intel (name, eax);
-
- /* This spells out "AuthenticAMD". */
- if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
- return handle_amd (name);
-
- // XXX Fill in more vendors.
+ if (name >= _SC_LEVEL1_ICACHE_SIZE && name <= _SC_LEVEL4_CACHE_LINESIZE)
+ return __cache_sysconf (name);
- /* CPU not known, we have no information. */
- return 0;
+ return linux_sysconf (name);
}
/* Now the generic Linux version. */
-------------- next part --------------
simple_memcpy builtin_memcpy memcpy
Length 1, alignment 0/ 0: 10 30 30
Length 1, alignment 0/ 0: 10 30 30
Length 1, alignment 0/ 0: 10 30 30
Length 1, alignment 0/ 0: 10 30 30
Length 2, alignment 0/ 0: 20 30 30
Length 2, alignment 1/ 0: 20 30 30
Length 2, alignment 0/ 1: 10 30 30
Length 2, alignment 1/ 1: 10 30 30
Length 4, alignment 0/ 0: 20 140 140
Length 4, alignment 2/ 0: 20 150 140
Length 4, alignment 0/ 2: 20 160 160
Length 4, alignment 2/ 2: 20 150 140
Length 8, alignment 0/ 0: 30 150 140
Length 8, alignment 3/ 0: 30 140 140
Length 8, alignment 0/ 3: 40 150 140
Length 8, alignment 3/ 3: 30 140 140
Length 16, alignment 0/ 0: 120 140 140
Length 16, alignment 4/ 0: 120 140 140
Length 16, alignment 0/ 4: 110 140 140
Length 16, alignment 4/ 4: 110 140 140
Length 32, alignment 0/ 0: 180 170 170
Length 32, alignment 5/ 0: 190 170 170
Length 32, alignment 0/ 5: 200 190 190
Length 32, alignment 5/ 5: 200 170 180
Length 64, alignment 0/ 0: 290 70 70
Length 64, alignment 6/ 0: 360 70 70
Length 64, alignment 0/ 6: 350 230 240
Length 64, alignment 6/ 6: 350 200 200
Length 128, alignment 0/ 0: 470 80 80
Length 128, alignment 7/ 0: 470 100 100
Length 128, alignment 0/ 7: 550 300 300
Length 128, alignment 7/ 7: 470 210 210
Length 256, alignment 0/ 0: 900 130 120
Length 256, alignment 8/ 0: 900 110 110
Length 256, alignment 0/ 8: 1100 210 210
Length 256, alignment 8/ 8: 900 110 110
Length 512, alignment 0/ 0: 1750 210 200
Length 512, alignment 9/ 0: 1750 420 410
Length 512, alignment 0/ 9: 1750 790 790
Length 512, alignment 9/ 9: 1750 380 380
Length 1024, alignment 0/ 0: 3460 320 310
Length 1024, alignment 10/ 0: 3460 780 780
Length 1024, alignment 0/10: 3460 1350 1350
Length 1024, alignment 10/10: 3460 490 490
Length 2048, alignment 0/ 0: 6870 530 520
Length 2048, alignment 11/ 0: 6870 1500 1490
Length 2048, alignment 0/11: 6870 2480 2470
Length 2048, alignment 11/11: 6870 710 700
Length 4096, alignment 0/ 0: 13700 930 930
Length 4096, alignment 12/ 0: 13700 3240 3240
Length 4096, alignment 0/12: 13700 4720 4720
Length 4096, alignment 12/12: 13700 1160 1160
Length 8192, alignment 0/ 0: 27350 1790 1780
Length 8192, alignment 13/ 0: 27350 6480 6490
Length 8192, alignment 0/13: 27350 9460 9460
Length 8192, alignment 13/13: 27350 1910 1910
Length 16384, alignment 0/ 0: 54660 4450 4080
Length 16384, alignment 14/ 0: 54660 12920 12960
Length 16384, alignment 0/14: 72770 19160 19160
Length 16384, alignment 14/14: 54660 4170 4180
Length 32768, alignment 0/ 0: 109270 16830 16830
Length 32768, alignment 15/ 0: 109280 26590 26980
Length 32768, alignment 0/15: 140370 38510 38510
Length 32768, alignment 15/15: 109270 16540 16540
Length 65536, alignment 0/ 0: 218500 33030 33200
Length 65536, alignment 16/ 0: 218500 32950 32790
Length 65536, alignment 0/16: 161460 28680 28680
Length 65536, alignment 16/16: 131050 19860 19800
Length 0, alignment 0/ 0: -40 0 0
Length 0, alignment 0/ 0: -40 -30 0
Length 0, alignment 0/ 0: -40 -30 -30
Length 0, alignment 0/ 0: -40 -30 -30
Length 1, alignment 0/ 0: -40 -30 -30
Length 1, alignment 1/ 0: -40 -30 -30
Length 1, alignment 0/ 1: -40 -30 -30
Length 1, alignment 1/ 1: -40 -30 -30
Length 2, alignment 0/ 0: -40 -30 -30
Length 2, alignment 2/ 0: -40 -30 -30
Length 2, alignment 0/ 2: -40 -30 -30
Length 2, alignment 2/ 2: -40 -30 -30
Length 3, alignment 0/ 0: 0 -30 -30
Length 3, alignment 3/ 0: -40 -30 -30
Length 3, alignment 0/ 3: -40 -30 -30
Length 3, alignment 3/ 3: -40 -30 -30
Length 4, alignment 0/ 0: -30 40 40
Length 4, alignment 4/ 0: -30 40 40
Length 4, alignment 0/ 4: -40 40 40
Length 4, alignment 4/ 4: -40 40 40
Length 5, alignment 0/ 0: 0 40 40
Length 5, alignment 5/ 0: -30 40 40
Length 5, alignment 0/ 5: -30 40 40
Length 5, alignment 5/ 5: -30 40 40
Length 6, alignment 0/ 0: 0 40 40
Length 6, alignment 6/ 0: -30 40 40
Length 6, alignment 0/ 6: -30 40 40
Length 6, alignment 6/ 6: -30 40 40
Length 7, alignment 0/ 0: 0 40 40
Length 7, alignment 7/ 0: 0 40 40
Length 7, alignment 0/ 7: 0 40 40
Length 7, alignment 7/ 7: 0 40 40
Length 8, alignment 0/ 0: 0 40 40
Length 8, alignment 8/ 0: 0 40 40
Length 8, alignment 0/ 8: 0 40 40
Length 8, alignment 8/ 8: 0 40 40
Length 9, alignment 0/ 0: 0 40 40
Length 9, alignment 9/ 0: 0 40 40
Length 9, alignment 0/ 9: 0 40 40
Length 9, alignment 9/ 9: 0 40 40
Length 10, alignment 0/ 0: 0 40 40
Length 10, alignment 10/ 0: 0 40 40
Length 10, alignment 0/10: 0 40 40
Length 10, alignment 10/10: 0 40 40
Length 11, alignment 0/ 0: 0 40 40
Length 11, alignment 11/ 0: 0 40 40
Length 11, alignment 0/11: 0 40 40
Length 11, alignment 11/11: 0 40 40
Length 12, alignment 0/ 0: 10 40 40
Length 12, alignment 12/ 0: 10 40 40
Length 12, alignment 0/12: 10 40 40
Length 12, alignment 12/12: 10 40 40
Length 13, alignment 0/ 0: 10 40 40
Length 13, alignment 13/ 0: 10 40 40
Length 13, alignment 0/13: 10 40 40
Length 13, alignment 13/13: 10 40 40
Length 14, alignment 0/ 0: 20 40 40
Length 14, alignment 14/ 0: 10 40 40
Length 14, alignment 0/14: 20 40 40
Length 14, alignment 14/14: 20 40 40
Length 15, alignment 0/ 0: 10 40 40
Length 15, alignment 15/ 0: 10 40 40
Length 15, alignment 0/15: 10 40 40
Length 15, alignment 15/15: 10 40 40
Length 16, alignment 0/ 0: 10 40 40
Length 16, alignment 16/ 0: 20 40 40
Length 16, alignment 0/16: 20 40 40
Length 16, alignment 16/16: 30 40 40
Length 17, alignment 0/ 0: 20 40 40
Length 17, alignment 17/ 0: 30 40 40
Length 17, alignment 0/17: 30 40 40
Length 17, alignment 17/17: 20 40 40
Length 18, alignment 0/ 0: 20 40 40
Length 18, alignment 18/ 0: 30 40 40
Length 18, alignment 0/18: 30 40 40
Length 18, alignment 18/18: 30 40 40
Length 19, alignment 0/ 0: 30 50 40
Length 19, alignment 19/ 0: 30 50 40
Length 19, alignment 0/19: 30 50 40
Length 19, alignment 19/19: 40 50 40
Length 20, alignment 0/ 0: 30 50 50
Length 20, alignment 20/ 0: 30 50 50
Length 20, alignment 0/20: 30 50 50
Length 20, alignment 20/20: 40 50 50
Length 21, alignment 0/ 0: 30 50 50
Length 21, alignment 21/ 0: 40 50 50
Length 21, alignment 0/21: 40 50 50
Length 21, alignment 21/21: 40 50 50
Length 22, alignment 0/ 0: 30 50 50
Length 22, alignment 22/ 0: 40 50 50
Length 22, alignment 0/22: 40 50 50
Length 22, alignment 22/22: 40 50 50
Length 23, alignment 0/ 0: 40 50 50
Length 23, alignment 23/ 0: 40 50 50
Length 23, alignment 0/23: 40 50 50
Length 23, alignment 23/23: 40 50 50
Length 24, alignment 0/ 0: 30 50 50
Length 24, alignment 24/ 0: 40 50 50
Length 24, alignment 0/24: 50 50 50
Length 24, alignment 24/24: 50 50 50
Length 25, alignment 0/ 0: 30 50 50
Length 25, alignment 25/ 0: 50 50 50
Length 25, alignment 0/25: 50 50 50
Length 25, alignment 25/25: 50 50 50
Length 26, alignment 0/ 0: 40 50 50
Length 26, alignment 26/ 0: 50 50 50
Length 26, alignment 0/26: 50 50 50
Length 26, alignment 26/26: 50 50 50
Length 27, alignment 0/ 0: 40 50 50
Length 27, alignment 27/ 0: 60 50 50
Length 27, alignment 0/27: 60 50 50
Length 27, alignment 27/27: 50 50 50
Length 28, alignment 0/ 0: 40 50 50
Length 28, alignment 28/ 0: 60 50 50
Length 28, alignment 0/28: 60 50 50
Length 28, alignment 28/28: 60 50 50
Length 29, alignment 0/ 0: 40 60 50
Length 29, alignment 29/ 0: 60 60 50
Length 29, alignment 0/29: 60 60 50
Length 29, alignment 29/29: 60 60 50
Length 30, alignment 0/ 0: 40 60 60
Length 30, alignment 30/ 0: 70 60 60
Length 30, alignment 0/30: 70 60 60
Length 30, alignment 30/30: 60 60 60
Length 31, alignment 0/ 0: 40 60 60
Length 31, alignment 31/ 0: 70 60 60
Length 31, alignment 0/31: 70 60 60
Length 31, alignment 31/31: 60 60 60
Length 48, alignment 0/ 0: 80 60 60
Length 48, alignment 3/ 0: 120 60 60
Length 48, alignment 0/ 3: 150 120 120
Length 48, alignment 3/ 3: 120 120 120
Length 80, alignment 0/ 0: 140 60 60
Length 80, alignment 5/ 0: 140 70 70
Length 80, alignment 0/ 5: 170 100 100
Length 80, alignment 5/ 5: 140 60 60
Length 96, alignment 0/ 0: 170 0 0
Length 96, alignment 6/ 0: 170 0 0
Length 96, alignment 0/ 6: 190 120 120
Length 96, alignment 6/ 6: 170 80 80
Length 112, alignment 0/ 0: 200 60 60
Length 112, alignment 7/ 0: 200 70 80
Length 112, alignment 0/ 7: 250 110 110
Length 112, alignment 7/ 7: 200 60 60
Length 144, alignment 0/ 0: 270 70 70
Length 144, alignment 9/ 0: 270 100 100
Length 144, alignment 0/ 9: 270 190 190
Length 144, alignment 9/ 9: 270 130 130
Length 160, alignment 0/ 0: 300 20 20
Length 160, alignment 10/ 0: 300 30 40
Length 160, alignment 0/10: 300 210 200
Length 160, alignment 10/10: 300 140 140
Length 176, alignment 0/ 0: 330 80 70
Length 176, alignment 11/ 0: 330 110 110
Length 176, alignment 0/11: 410 210 210
Length 176, alignment 11/11: 330 130 130
Length 192, alignment 0/ 0: 360 30 10
Length 192, alignment 12/ 0: 360 50 50
Length 192, alignment 0/12: 360 220 220
Length 192, alignment 12/12: 360 150 150
Length 208, alignment 0/ 0: 400 80 80
Length 208, alignment 13/ 0: 400 130 120
Length 208, alignment 0/13: 400 180 180
Length 208, alignment 13/13: 400 80 80
Length 224, alignment 0/ 0: 430 10 20
Length 224, alignment 14/ 0: 430 70 80
Length 224, alignment 0/14: 430 210 200
Length 224, alignment 14/14: 430 110 90
Length 240, alignment 0/ 0: 460 80 80
Length 240, alignment 15/ 0: 460 130 120
Length 240, alignment 0/15: 460 200 200
Length 240, alignment 15/15: 460 80 80
Length 272, alignment 0/ 0: 520 100 80
Length 272, alignment 17/ 0: 530 160 150
Length 272, alignment 0/17: 520 270 270
Length 272, alignment 17/17: 520 140 140
Length 288, alignment 0/ 0: 560 30 30
Length 288, alignment 18/ 0: 560 80 70
Length 288, alignment 0/18: 560 290 290
Length 288, alignment 18/18: 560 150 150
Length 304, alignment 0/ 0: 590 90 90
Length 304, alignment 19/ 0: 590 160 150
Length 304, alignment 0/19: 590 290 290
Length 304, alignment 19/19: 590 160 160
Length 320, alignment 0/ 0: 620 40 40
Length 320, alignment 20/ 0: 620 110 100
Length 320, alignment 0/20: 620 300 300
Length 320, alignment 20/20: 620 180 180
Length 336, alignment 0/ 0: 650 110 110
Length 336, alignment 21/ 0: 650 190 180
Length 336, alignment 0/21: 650 270 260
Length 336, alignment 21/21: 650 110 110
Length 352, alignment 0/ 0: 680 60 50
Length 352, alignment 22/ 0: 680 130 130
Length 352, alignment 0/22: 680 290 280
Length 352, alignment 22/22: 680 140 140
Length 368, alignment 0/ 0: 720 120 120
Length 368, alignment 23/ 0: 720 200 190
Length 368, alignment 0/23: 720 280 280
Length 368, alignment 23/23: 720 120 130
Length 384, alignment 0/ 0: 750 60 60
Length 384, alignment 24/ 0: 750 60 60
Length 384, alignment 0/24: 750 160 150
Length 384, alignment 24/24: 750 60 60
Length 400, alignment 0/ 0: 780 130 130
Length 400, alignment 25/ 0: 780 230 220
Length 400, alignment 0/25: 780 350 350
Length 400, alignment 25/25: 780 160 160
Length 416, alignment 0/ 0: 810 60 60
Length 416, alignment 26/ 0: 810 170 150
Length 416, alignment 0/26: 810 360 360
Length 416, alignment 26/26: 810 180 170
Length 432, alignment 0/ 0: 840 130 130
Length 432, alignment 27/ 0: 840 230 220
Length 432, alignment 0/27: 840 370 360
Length 432, alignment 27/27: 840 160 160
Length 448, alignment 0/ 0: 880 70 70
Length 448, alignment 28/ 0: 880 190 180
Length 448, alignment 0/28: 880 380 380
Length 448, alignment 28/28: 880 180 180
Length 464, alignment 0/ 0: 920 140 130
Length 464, alignment 29/ 0: 910 260 250
Length 464, alignment 0/29: 910 350 350
Length 464, alignment 29/29: 910 140 130
Length 480, alignment 0/ 0: 940 80 70
Length 480, alignment 30/ 0: 940 190 190
Length 480, alignment 0/30: 940 360 360
Length 480, alignment 30/30: 940 150 150
Length 496, alignment 0/ 0: 970 140 140
Length 496, alignment 31/ 0: 970 260 250
Length 496, alignment 0/31: 970 360 360
Length 496, alignment 31/31: 970 140 140
Length 4096, alignment 0/ 0: 8170 510 510
-------------- next part --------------
simple_memcpy builtin_memcpy memcpy
Length 1, alignment 0/ 0: 10 20 10
Length 1, alignment 0/ 0: 10 20 10
Length 1, alignment 0/ 0: 10 20 10
Length 1, alignment 0/ 0: 10 20 10
Length 2, alignment 0/ 0: 10 20 20
Length 2, alignment 1/ 0: 10 20 20
Length 2, alignment 0/ 1: 10 20 20
Length 2, alignment 1/ 1: 20 20 20
Length 4, alignment 0/ 0: 20 20 10
Length 4, alignment 2/ 0: 20 20 10
Length 4, alignment 0/ 2: 20 20 10
Length 4, alignment 2/ 2: 20 20 10
Length 8, alignment 0/ 0: 30 20 20
Length 8, alignment 3/ 0: 30 20 20
Length 8, alignment 0/ 3: 40 20 20
Length 8, alignment 3/ 3: 30 20 20
Length 16, alignment 0/ 0: 120 20 20
Length 16, alignment 4/ 0: 110 20 20
Length 16, alignment 0/ 4: 110 20 20
Length 16, alignment 4/ 4: 120 20 20
Length 32, alignment 0/ 0: 160 30 30
Length 32, alignment 5/ 0: 190 30 40
Length 32, alignment 0/ 5: 190 70 70
Length 32, alignment 5/ 5: 190 60 60
Length 64, alignment 0/ 0: 290 50 40
Length 64, alignment 6/ 0: 350 50 40
Length 64, alignment 0/ 6: 350 120 110
Length 64, alignment 6/ 6: 340 110 120
Length 128, alignment 0/ 0: 470 50 60
Length 128, alignment 7/ 0: 470 90 80
Length 128, alignment 0/ 7: 550 170 170
Length 128, alignment 7/ 7: 470 110 100
Length 256, alignment 0/ 0: 900 80 80
Length 256, alignment 8/ 0: 900 80 80
Length 256, alignment 0/ 8: 1100 190 190
Length 256, alignment 8/ 8: 900 80 80
Length 512, alignment 0/ 0: 1750 130 130
Length 512, alignment 9/ 0: 1750 350 350
Length 512, alignment 0/ 9: 1750 590 600
Length 512, alignment 9/ 9: 1750 190 190
Length 1024, alignment 0/ 0: 3460 260 260
Length 1024, alignment 10/ 0: 3460 720 720
Length 1024, alignment 0/10: 3460 1150 1150
Length 1024, alignment 10/10: 3460 290 290
Length 2048, alignment 0/ 0: 6870 600 590
Length 2048, alignment 11/ 0: 6870 1510 1510
Length 2048, alignment 0/11: 6870 5180 5190
Length 2048, alignment 11/11: 6870 630 630
Length 4096, alignment 0/ 0: 13700 1080 1070
Length 4096, alignment 12/ 0: 13700 3470 3460
Length 4096, alignment 0/12: 13700 10360 10350
Length 4096, alignment 12/12: 13700 1100 1100
Length 8192, alignment 0/ 0: 27350 2040 2030
Length 8192, alignment 13/ 0: 27350 6900 6900
Length 8192, alignment 0/13: 27350 21150 21150
Length 8192, alignment 13/13: 27350 2060 2060
Length 16384, alignment 0/ 0: 54660 4250 4250
Length 16384, alignment 14/ 0: 54660 13850 13810
Length 16384, alignment 0/14: 72950 42780 42780
Length 16384, alignment 14/14: 54660 4320 4400
Length 32768, alignment 0/ 0: 109280 16010 16020
Length 32768, alignment 15/ 0: 109280 28350 28320
Length 32768, alignment 0/15: 140440 58710 58700
Length 32768, alignment 15/15: 109270 16870 16980
Length 65536, alignment 0/ 0: 218500 31030 30970
Length 65536, alignment 16/ 0: 131060 18580 18680
Length 65536, alignment 0/16: 158140 29570 29650
Length 65536, alignment 16/16: 131050 18550 18430
Length 0, alignment 0/ 0: 0 60 0
Length 0, alignment 0/ 0: -40 -40 0
Length 0, alignment 0/ 0: -40 -40 0
Length 0, alignment 0/ 0: -40 -40 -40
Length 1, alignment 0/ 0: -40 0 -40
Length 1, alignment 1/ 0: -40 -40 0
Length 1, alignment 0/ 1: -40 -40 -40
Length 1, alignment 1/ 1: -40 0 -40
Length 2, alignment 0/ 0: -40 10 0
Length 2, alignment 2/ 0: -40 0 0
Length 2, alignment 0/ 2: -40 0 -40
Length 2, alignment 2/ 2: -40 -40 -40
Length 3, alignment 0/ 0: 20 10 -40
Length 3, alignment 3/ 0: -40 -40 0
Length 3, alignment 0/ 3: 2380 0 0
Length 3, alignment 3/ 3: -40 -40 -40
Length 4, alignment 0/ 0: -40 0 -40
Length 4, alignment 4/ 0: -40 -40 -40
Length 4, alignment 0/ 4: -40 0 -40
Length 4, alignment 4/ 4: 0 -40 0
Length 5, alignment 0/ 0: 20 0 -40
Length 5, alignment 5/ 0: 10 0 -40
Length 5, alignment 0/ 5: -30 -40 -40
Length 5, alignment 5/ 5: -30 0 -40
Length 6, alignment 0/ 0: 0 10 10
Length 6, alignment 6/ 0: 0 -40 -40
Length 6, alignment 0/ 6: 0 -40 -40
Length 6, alignment 6/ 6: 0 -40 -40
Length 7, alignment 0/ 0: 0 10 -40
Length 7, alignment 7/ 0: 0 -40 -40
Length 7, alignment 0/ 7: 0 0 -40
Length 7, alignment 7/ 7: 0 -40 -40
Length 8, alignment 0/ 0: 0 10 -40
Length 8, alignment 8/ 0: 0 -40 -40
Length 8, alignment 0/ 8: 0 -40 -40
Length 8, alignment 8/ 8: 0 0 -40
Length 9, alignment 0/ 0: 0 10 -40
Length 9, alignment 9/ 0: 0 0 -40
Length 9, alignment 0/ 9: 0 -40 -40
Length 9, alignment 9/ 9: 0 -40 -40
Length 10, alignment 0/ 0: 0 10 -40
Length 10, alignment 10/ 0: 10 -40 -40
Length 10, alignment 0/10: 0 -40 -40
Length 10, alignment 10/10: 0 -40 -40
Length 11, alignment 0/ 0: 0 10 -40
Length 11, alignment 11/ 0: 10 0 -40
Length 11, alignment 0/11: 10 -40 -40
Length 11, alignment 11/11: 0 -40 -40
Length 12, alignment 0/ 0: 10 40 -40
Length 12, alignment 12/ 0: 10 -40 -40
Length 12, alignment 0/12: 0 -40 -40
Length 12, alignment 12/12: 10 -40 -40
Length 13, alignment 0/ 0: 10 10 -40
Length 13, alignment 13/ 0: 10 0 -40
Length 13, alignment 0/13: 20 0 -40
Length 13, alignment 13/13: 20 -40 -40
Length 14, alignment 0/ 0: 10 20 -40
Length 14, alignment 14/ 0: 10 -40 0
Length 14, alignment 0/14: 20 0 -40
Length 14, alignment 14/14: 20 -40 -40
Length 15, alignment 0/ 0: 10 10 -40
Length 15, alignment 15/ 0: 10 0 -40
Length 15, alignment 0/15: 10 -40 -40
Length 15, alignment 15/15: 10 -40 -40
Length 16, alignment 0/ 0: 20 10 -40
Length 16, alignment 16/ 0: 30 -30 0
Length 16, alignment 0/16: 20 -30 -40
Length 16, alignment 16/16: 20 -30 -40
Length 17, alignment 0/ 0: 20 10 0
Length 17, alignment 17/ 0: 20 -30 -40
Length 17, alignment 0/17: 20 -30 -40
Length 17, alignment 17/17: 30 -30 -40
Length 18, alignment 0/ 0: 20 -30 -40
Length 18, alignment 18/ 0: 30 -30 -40
Length 18, alignment 0/18: 30 0 -40
Length 18, alignment 18/18: 30 -30 -40
Length 19, alignment 0/ 0: 20 20 0
Length 19, alignment 19/ 0: 30 0 0
Length 19, alignment 0/19: 30 0 0
Length 19, alignment 19/19: 30 -30 -30
Length 20, alignment 0/ 0: 20 20 0
Length 20, alignment 20/ 0: 40 0 -40
Length 20, alignment 0/20: 30 -30 -40
Length 20, alignment 20/20: 30 -30 -40
Length 21, alignment 0/ 0: 30 10 0
Length 21, alignment 21/ 0: 40 -30 0
Length 21, alignment 0/21: 30 -30 -40
Length 21, alignment 21/21: 40 -30 -40
Length 22, alignment 0/ 0: 30 10 -30
Length 22, alignment 22/ 0: 40 0 -30
Length 22, alignment 0/22: 40 0 -30
Length 22, alignment 22/22: 30 -30 -30
Length 23, alignment 0/ 0: 30 10 -30
Length 23, alignment 23/ 0: 50 -30 0
Length 23, alignment 0/23: 30 -30 0
Length 23, alignment 23/23: 40 -30 0
Length 24, alignment 0/ 0: 30 50 10
Length 24, alignment 24/ 0: 50 -30 10
Length 24, alignment 0/24: 40 -30 -40
Length 24, alignment 24/24: 50 0 -40
Length 25, alignment 0/ 0: 40 20 -40
Length 25, alignment 25/ 0: 50 0 -40
Length 25, alignment 0/25: 50 -30 -40
Length 25, alignment 25/25: 50 -30 -40
Length 26, alignment 0/ 0: 40 30 -40
Length 26, alignment 26/ 0: 50 -30 0
Length 26, alignment 0/26: 50 -30 -40
Length 26, alignment 26/26: 40 -30 -40
Length 27, alignment 0/ 0: 40 20 -30
Length 27, alignment 27/ 0: 60 -30 -30
Length 27, alignment 0/27: 50 -30 0
Length 27, alignment 27/27: 50 -30 -30
Length 28, alignment 0/ 0: 40 30 -30
Length 28, alignment 28/ 0: 60 0 -30
Length 28, alignment 0/28: 60 -30 -30
Length 28, alignment 28/28: 60 -30 -30
Length 29, alignment 0/ 0: 40 10 -30
Length 29, alignment 29/ 0: 60 0 -30
Length 29, alignment 0/29: 60 -30 -30
Length 29, alignment 29/29: 60 -30 -20
Length 30, alignment 0/ 0: 40 10 -30
Length 30, alignment 30/ 0: 70 0 0
Length 30, alignment 0/30: 70 -30 -30
Length 30, alignment 30/30: 70 -30 -30
Length 31, alignment 0/ 0: 40 10 -30
Length 31, alignment 31/ 0: 70 -30 -30
Length 31, alignment 0/31: 70 -30 -30
Length 31, alignment 31/31: 50 -30 -30
Length 48, alignment 0/ 0: 80 70 10
Length 48, alignment 3/ 0: 120 10 0
Length 48, alignment 0/ 3: 150 10 10
Length 48, alignment 3/ 3: 120 0 0
Length 80, alignment 0/ 0: 140 0 0
Length 80, alignment 5/ 0: 140 0 0
Length 80, alignment 0/ 5: 170 20 20
Length 80, alignment 5/ 5: 140 0 0
Length 96, alignment 0/ 0: 170 80 10
Length 96, alignment 6/ 0: 170 10 10
Length 96, alignment 0/ 6: 190 30 30
Length 96, alignment 6/ 6: 170 0 0
Length 112, alignment 0/ 0: 200 0 0
Length 112, alignment 7/ 0: 200 0 0
Length 112, alignment 0/ 7: 240 30 30
Length 112, alignment 7/ 7: 200 0 0
Length 144, alignment 0/ 0: 270 0 0
Length 144, alignment 9/ 0: 280 10 10
Length 144, alignment 0/ 9: 270 60 60
Length 144, alignment 9/ 9: 270 10 10
Length 160, alignment 0/ 0: 300 0 0
Length 160, alignment 10/ 0: 300 10 10
Length 160, alignment 0/10: 300 70 80
Length 160, alignment 10/10: 300 10 10
Length 176, alignment 0/ 0: 330 0 0
Length 176, alignment 11/ 0: 330 10 10
Length 176, alignment 0/11: 410 80 70
Length 176, alignment 11/11: 330 10 10
Length 192, alignment 0/ 0: 360 10 0
Length 192, alignment 12/ 0: 360 40 30
Length 192, alignment 0/12: 360 90 90
Length 192, alignment 12/12: 360 20 20
Length 208, alignment 0/ 0: 400 0 0
Length 208, alignment 13/ 0: 400 40 40
Length 208, alignment 0/13: 400 100 100
Length 208, alignment 13/13: 400 10 10
Length 224, alignment 0/ 0: 430 10 0
Length 224, alignment 14/ 0: 440 60 30
Length 224, alignment 0/14: 430 110 110
Length 224, alignment 14/14: 430 10 10
Length 240, alignment 0/ 0: 460 10 10
Length 240, alignment 15/ 0: 460 40 40
Length 240, alignment 0/15: 460 110 110
Length 240, alignment 15/15: 460 10 20
Length 272, alignment 0/ 0: 520 10 20
Length 272, alignment 17/ 0: 520 70 80
Length 272, alignment 0/17: 520 150 150
Length 272, alignment 17/17: 520 30 30
Length 288, alignment 0/ 0: 560 0 0
Length 288, alignment 18/ 0: 560 60 60
Length 288, alignment 0/18: 560 160 150
Length 288, alignment 18/18: 560 30 30
Length 304, alignment 0/ 0: 590 10 10
Length 304, alignment 19/ 0: 590 80 80
Length 304, alignment 0/19: 590 170 170
Length 304, alignment 19/19: 590 40 40
Length 320, alignment 0/ 0: 620 10 10
Length 320, alignment 20/ 0: 620 90 80
Length 320, alignment 0/20: 620 180 170
Length 320, alignment 20/20: 620 50 40
Length 336, alignment 0/ 0: 650 20 20
Length 336, alignment 21/ 0: 650 90 90
Length 336, alignment 0/21: 650 180 180
Length 336, alignment 21/21: 650 30 30
Length 352, alignment 0/ 0: 680 20 20
Length 352, alignment 22/ 0: 680 90 90
Length 352, alignment 0/22: 680 190 190
Length 352, alignment 22/22: 680 30 30
Length 368, alignment 0/ 0: 720 20 20
Length 368, alignment 23/ 0: 720 110 110
Length 368, alignment 0/23: 720 200 200
Length 368, alignment 23/23: 720 40 40
Length 384, alignment 0/ 0: 760 30 30
Length 384, alignment 24/ 0: 750 30 30
Length 384, alignment 0/24: 750 120 120
Length 384, alignment 24/24: 750 30 30
Length 400, alignment 0/ 0: 780 40 40
Length 400, alignment 25/ 0: 780 130 130
Length 400, alignment 0/25: 780 220 220
Length 400, alignment 25/25: 780 40 40
Length 416, alignment 0/ 0: 810 30 20
Length 416, alignment 26/ 0: 810 120 120
Length 416, alignment 0/26: 810 220 220
Length 416, alignment 26/26: 810 40 40
Length 432, alignment 0/ 0: 840 30 30
Length 432, alignment 27/ 0: 840 140 140
Length 432, alignment 0/27: 840 240 230
Length 432, alignment 27/27: 840 40 40
Length 448, alignment 0/ 0: 880 40 30
Length 448, alignment 28/ 0: 880 150 150
Length 448, alignment 0/28: 880 240 230
Length 448, alignment 28/28: 880 40 40
Length 464, alignment 0/ 0: 910 30 30
Length 464, alignment 29/ 0: 910 150 150
Length 464, alignment 0/29: 910 260 260
Length 464, alignment 29/29: 920 60 60
Length 480, alignment 0/ 0: 940 40 40
Length 480, alignment 30/ 0: 940 150 150
Length 480, alignment 0/30: 940 260 260
Length 480, alignment 30/30: 940 40 40
Length 496, alignment 0/ 0: 970 40 40
Length 496, alignment 31/ 0: 970 170 170
Length 496, alignment 0/31: 970 270 270
Length 496, alignment 31/31: 970 40 40
Length 4096, alignment 0/ 0: 8170 600 600
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