[PATCH] [BZ#2505] PPC32 should use lwsync where possible

[Segher Boessenkool]

Hi Steven,

I would love to review this, but I'm afraid I have no idea
what any of these macros are supposed to do.  Could you please
explain, preferably in code comments, or just point me to the
documentation (that I searched for, but could not find)?  Thanks.


Segher



On 3-apr-2006, at 22:06, Steven Munroe wrote:

> [BZ#2505]
>
> The currently PPC32 still uses (full) sync for atomic.h and
> lowlevellock.h to insure backward compatibility with older 32-bit PPC
> chips. This is penalizing the performance of 32-bit applications on  
> the
> newer 64-bit processors like 970, POWER4, and POWER5 which do  
> implement
> lwsync.
>
> With gcc-4.1, gcc will define _ARCH_PWR4 when -mcpu=[970, power4,
> power5,power5+]  is specified. This works with the --with-cpu=  
> configure
> option allow builds targeted for 64-bit hardware to include new
> instructions available on power4 and newer architecture levels.
>
> The attached patches will define macros to use lwsync if _ARCH_PWR4 is
> defined.
>
>
> 2006-04-03  Steven Munroe  <sjmunroe@us.ibm.com>
>
> 	[BZ #2505]
> 	* sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR4]:
> 	Define atomic_read_barrier and __ARCH_REL_INSTR using lwsync.
>
> diff -urN libc24-cvstip-20060331/sysdeps/powerpc/powerpc32/bits/ 
> atomic.h libc24/sysdeps/powerpc/powerpc32/bits/atomic.h
> --- libc24-cvstip-20060331/sysdeps/powerpc/powerpc32/bits/atomic.h	 
> 2004-09-08 00:16:09.000000000 -0500
> +++ libc24/sysdeps/powerpc/powerpc32/bits/atomic.h	2006-03-31  
> 17:33:32.598312040 -0600
> @@ -89,12 +89,27 @@
>  # define __arch_atomic_decrement_if_positive_64(mem) \
>      ({ abort (); (*mem)--; })
>
> +#ifdef _ARCH_PWR4
> +/*
> + * Newer powerpc64 processors support the new "light weight" sync  
> (lwsync)
> + * So if the build is using -mcpu=[power4,power5,power5+,970] we can
> + * safely use lwsync.
> + */
> +# define atomic_read_barrier()	__asm ("lwsync" ::: "memory")
> +/*
> + * "light weight" sync can also be used for the release barrier.
> + */
> +# ifndef UP
> +#  define __ARCH_REL_INSTR	"lwsync"
> +# endif
> +#else
>  /*
>   * Older powerpc32 processors don't support the new "light weight"
>   * sync (lwsync).  So the only safe option is to use normal sync
>   * for all powerpc32 applications.
>   */
>  # define atomic_read_barrier()	__asm ("sync" ::: "memory")
> +#endif
>
>  /*
>   * Include the rest of the atomic ops macros which are common to both
> 2006-04-03  Steven Munroe  <sjmunroe@us.ibm.com>
>
> 	[BZ #2505]
> 	* sysdeps/unix/sysv/linux/powerpc/lowlevellock.h [_ARCH_PWR4]:
> 	Define __lll_rel_instr using lwsync.
>
> diff -urN libc24-cvstip-20060331/nptl/sysdeps/unix/sysv/linux/ 
> powerpc/lowlevellock.h libc24/nptl/sysdeps/unix/sysv/linux/powerpc/ 
> lowlevellock.h
> --- libc24-cvstip-20060331/nptl/sysdeps/unix/sysv/linux/powerpc/ 
> lowlevellock.h	2006-02-17 12:44:33.000000000 -0600
> +++ libc24/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h	 
> 2006-03-31 17:32:54.997302072 -0600
> @@ -110,7 +110,21 @@
>  # define __lll_rel_instr	""
>  #else
>  # define __lll_acq_instr	"isync"
> -# define __lll_rel_instr	"sync"
> +# ifdef _ARCH_PWR4
> +/*
> + * Newer powerpc64 processors support the new "light weight" sync  
> (lwsync)
> + * So if the build is using -mcpu=[power4,power5,power5+,970] we can
> + * safely use lwsync.
> + */
> +#  define __lll_rel_instr	"lwsync"
> +# else
> +/*
> + * Older powerpc32 processors don't support the new "light weight"
> + * sync (lwsync).  So the only safe option is to use normal sync
> + * for all powerpc32 applications.
> + */
> +#  define __lll_rel_instr	"sync"
> +# endif
>  #endif
>
>  /* Set *futex to ID if it is 0, atomically.  Returns the old value */