Enable

Andreas Jaeger aj@suse.de
Mon Oct 4 04:32:00 GMT 1999


A few month ago there was a short discussion about __setfpucw and how
to portable set floating point exception _mask_ bits (I'm appending
two emails from that thread).  Geoff proposed to add two functions
`feenableexcept' and `fedisableexcept' to enable and disable
individual exceptions.  Zack proposed to implement the <ieeefp.h>
interface (btw. I don't think they're part of any standard - AFAIK
they're Sun specific).  I've added the exception control part from
Solaris 7 to explain the concept.

The discussion stopped without any results.  

David Munro  contacted me and asked for a FE_NUMERIC_ENV since he
only needs a certain subset of the masks for his numeric software:
> FE_NUMERIC_ENV   -- zero divide, overflow, invalid exceptions unmasked,
>                    all others masked
>                    plus rapid flush to zero on processors which implement
>                    IEEE 754 denormal in software (slowly)

David's suggestion leads to a minimal patch - but opens a can of worms
(everybody likes to have his favorite environment set).  I rather
would like to have a general solution and prefer Geoff's proposal.

I could try implement this - if we come to any agreement.

So what do you think?

Andreas

>From  <ieeefp.h>  (Solaris 7):
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/*
 * EXCEPTION CONTROL *****************************************
 *
 */

#define	fp_except	int

#define	FP_DISABLE	0	/* exception will be ignored */
#define	FP_ENABLE	1	/* exception will cause SIGFPE */
#define	FP_CLEAR	0	/* exception has not occurred */
#define	FP_SET		1	/* exception has occurred */

#if __i386_conditional

/*
 * There are six floating point exceptions, which can be individually
 * ENABLED (== 1) or DISABLED (== 0).  When an exception occurs
 * (ENABLED or not), the fact is noted by changing an associated
 * "sticky bit" from CLEAR (==0) to SET (==1).
 *
 * NOTE: the bit positions in fp_except are chosen to match those of
 * the 80*87 control word mask bits.  Although the 87 chips actually
 * ENABLE exceptions with a mask value of 0 (not 1, as on the 3b), it
 * is felt that switching these values may create more problems than
 * it solves.
 */

/* an fp_except can have the following (not exclusive) values: */
#define	FP_X_INV	0x01	/* invalid operation exception */
#define	FP_X_DNML	0x02	/* denormalization exception */
#define	FP_X_DZ		0x04	/* divide-by-zero exception */
#define	FP_X_OFL	0x08	/* overflow exception */
#define	FP_X_UFL	0x10	/* underflow exception */
#define	FP_X_IMP	0x20	/* imprecise (loss of precision) */

#endif

#if __sparc_conditional

/*
 * There are five floating-point exceptions, which can be individually
 * ENABLED (== 1) or DISABLED (== 0).  When an exception occurs
 * (ENABLED or not), the fact is noted by changing an associated
 * "sticky bit" from CLEAR (==0) to SET (==1).
 *
 * NOTE: the bit positions in an fp_except are chosen to match that in
 * the Trap Enable Mask of the FSR (Floating Point State Register).
 */

/* an fp_except can have the following (not exclusive) values: */
#define	FP_X_INV	0x10	/* invalid operation exception */
#define	FP_X_OFL	0x08	/* overflow exception */
#define	FP_X_UFL	0x04	/* underflow exception */
#define	FP_X_DZ		0x02	/* divide-by-zero exception */
#define	FP_X_IMP	0x01	/* imprecise (loss of precision) */

#endif

#if defined(__STDC__)
extern fp_except fpgetmask(void);		/* current exception mask */
extern fp_except fpsetmask(fp_except);		/* set mask, return previous */
extern fp_except fpgetsticky(void);		/* return logged exceptions */
extern fp_except fpsetsticky(fp_except);	/* change logged exceptions */

#else
extern fp_except fpgetmask();	/* current exception mask */
extern fp_except fpsetmask();	/* set mask, return previous */
extern fp_except fpgetsticky();	/* return logged exceptions */
extern fp_except fpsetsticky();	/* change logged exceptions */

#endif
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



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