GNU C Library master sources branch hjl/cache/master created. glibc-2.23-323-g9a39358

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commit 9a39358a353ff1906c728096bb343bb31a850d6c
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Fri May 13 13:26:37 2016 -0700

    Count number of logical processors sharing L2 cache
    
    For Intel processors, we should count number of available logical
    processors sharing L2 cache for non-inclusive L2 and L3 caches.
    
    	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
    	available logical processors sharing L2 cache for Intel
    	processors.

diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 8408624..6fe41be 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -499,12 +499,18 @@ init_cacheinfo (void)
       level  = 3;
       shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
 
+      /* Number of logical processors sharing L2 cache.  */
+      int logical_threads_l2;
+
       if (shared <= 0)
 	{
 	  /* Try L2 otherwise.  */
 	  level  = 2;
 	  shared = core;
+	  logical_threads_l2 = -1;
 	}
+      else
+	logical_threads_l2 = 0;
 
       /* Figure out the number of logical threads that share the
 	 highest cache level.  */
@@ -526,6 +532,11 @@ init_cacheinfo (void)
 		 assume there is no such information.  */
 	      if ((eax & 0x1f) == 0)
 		goto intel_bug_no_cache_info;
+
+	      /* Get maximum number of logical processors sharing L2
+		 cache.  */
+	      if (logical_threads_l2 == 0 && ((eax >> 5) & 0x7) == 2)
+		logical_threads_l2 = (eax >> 14) & 0x3ff;
 	    }
 	  while (((eax >> 5) & 0x7) != level);
 
@@ -551,6 +562,19 @@ init_cacheinfo (void)
 		  int type = ecx & 0xff0;
 		  if (shipped == 0 || type == 0)
 		    break;
+		  else if (type == 0x100)
+		    {
+		      if (logical_threads_l2 > 0)
+			{
+			  int count_mask;
+
+			  /* Compute count mask.  */
+			  asm ("bsr %1, %0"
+			       : "=r" (count_mask) : "g" (threads));
+			  count_mask = ~(-1 << (count_mask + 1));
+			  logical_threads_l2 = (shipped - 1) & count_mask;
+			}
+		    }
 		  else if (type == 0x200)
 		    {
 		      int count_mask;
@@ -601,7 +625,11 @@ init_cacheinfo (void)
 
       /* Account for non-inclusive L2 and L3 caches.  */
       if (level == 3 && !inclusive_cache)
-	shared += core;
+	{
+	  if (logical_threads_l2 > 0)
+	    core /= (logical_threads_l2 + 1);
+	  shared += core;
+	}
     }
   /* This spells out "AuthenticAMD".  */
   else if (is_amd)

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