GNU C Library master sources branch master updated. glibc-2.22-563-gdb4855b

macro@sourceware.org macro@sourceware.org
Sat Nov 28 11:05:00 GMT 2015


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commit db4855bf0c6fa25f0e3e62c60deb43ffe527b07c
Author: Maciej W. Rozycki <macro@imgtec.com>
Date:   Sat Nov 28 11:01:16 2015 +0000

    MIPS: Wire FCSR.ABS2008 to FCSR.NAN2008
    
    Revision 3.50 of the MIPS architecture defined FCSR ABS2008 and NAN2008
    bits as optionally read/write [1][2].  No hardware implementation has
    ever made use of this feature though.  For example the first processor
    to implement these bits, the MIPS32r3 proAptiv core, has both bits
    read-only, hardwired to 1 [3].  And as from revision 5.03 of the MIPS
    architecture the bits are required to be read-only, preset by hardware
    [4][5].  Additionally all hardware implementations in existence have the
    bits hardwired both to the same value, either of `0' and `1'.
    
    These bits may still be read/write or hardwired to opposite values in
    simulated hardware implementations such as QEMU or the FPU emulator
    included with the Linux kernel.  However to match real hardware
    implementations the Linux kernel will set FCSR ABS2008 and NAN2008 bits
    both to the same value where possible, reflecting the setting of the
    EF_MIPS_NAN2008 ELF file header bit.
    
    Therefore update the bit patterns in macro definitions we use for the
    control word, in the 2008-NaN encoding mode, so that both bits have the
    same value in a given bit pattern.  Additionally mark the FCSR ABS2008
    bit as reserved, so that high-level calls to change the control word do
    not affect the bit.
    
    This covers the regular FPU configurations, only leaving exotic corner
    cases with the value of FCSR control word initially set by the kernel
    different to what our code thinks it is.  To address the remaining cases
    the AT_FPUCW auxiliary vector entry would have to be implemented in the
    Linux kernel, which currently is not.
    
    References:
    
    [1] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
        MIPS32 Architecture", MIPS Technologies, Inc., Document Number:
        MD00082, Revision 3.50, September 20, 2012, Table 5.5 "FCSR Register
        Field Descriptions", p. 80
    
    [2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
        MIPS64 Architecture", MIPS Technologies, Inc., Document Number:
        MD00083, Revision 3.50, September 20, 2012, Table 5.5 "FCSR Register
        Field Descriptions", p. 82
    
    [3] "MIPS32 proAptiv Multiprocessing System Software User's Manual",
        MIPS Technologies, Inc., Document Number: MD00878, Revision 01.22,
        May 14, 2013, Table 12.10 "FCSR Bit Field Descriptions", p. 570
    
    [4] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
        MIPS32 Architecture", MIPS Technologies, Inc., Document Number:
        MD00082, Revision 5.03, Sept. 9, 2013, Table 5.7 "FCSR Register
        Field Descriptions", p. 82
    
    [5] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
        MIPS64 Architecture", MIPS Technologies, Inc., Document Number:
        MD00083, Revision 5.03, Sept. 9, 2013, Table 5.7 "FCSR Register
        Field Descriptions", p. 84
    
    	* sysdeps/mips/fpu_control.h (_FPU_RESERVED): Include ABS2008.
    	(_FPU_DEFAULT, _FPU_IEEE) [__mips_nan2008]: Set ABS2008.

diff --git a/ChangeLog b/ChangeLog
index 4146d99..d4dc8a4 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2015-11-28  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* sysdeps/mips/fpu_control.h (_FPU_RESERVED): Include ABS2008.
+	(_FPU_DEFAULT, _FPU_IEEE) [__mips_nan2008]: Set ABS2008.
+
 2015-11-27  Carlos O'Donell  <carlos@redhat.com>
 
 	[BZ #14259]
diff --git a/sysdeps/mips/fpu_control.h b/sysdeps/mips/fpu_control.h
index cfb4e6a..3347c28 100644
--- a/sysdeps/mips/fpu_control.h
+++ b/sysdeps/mips/fpu_control.h
@@ -93,20 +93,20 @@ extern fpu_control_t __fpu_control;
 /* Mask for rounding control.  */
 #define _FPU_RC_MASK	0x3
 
-#define _FPU_RESERVED 0xfe840000  /* Reserved bits in cw, incl NAN2008.  */
+#define _FPU_RESERVED 0xfe8c0000  /* Reserved bits in cw, incl ABS/NAN2008.  */
 
 
 /* The fdlibm code requires strict IEEE double precision arithmetic,
    and no interrupts for exceptions, rounding to nearest.  */
 #ifdef __mips_nan2008
-# define _FPU_DEFAULT 0x00040000
+# define _FPU_DEFAULT 0x000C0000
 #else
 # define _FPU_DEFAULT 0x00000000
 #endif
 
 /* IEEE: same as above, but exceptions.  */
 #ifdef __mips_nan2008
-# define _FPU_IEEE    0x00040F80
+# define _FPU_IEEE    0x000C0F80
 #else
 # define _FPU_IEEE    0x00000F80
 #endif

-----------------------------------------------------------------------

Summary of changes:
 ChangeLog                  |    5 +++++
 sysdeps/mips/fpu_control.h |    6 +++---
 2 files changed, 8 insertions(+), 3 deletions(-)


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