[Bug string/23709] glibc 2.25 lacks sse2 optimized strstr()

[adhemerval.zanella at linaro dot org]

https://sourceware.org/bugzilla/show_bug.cgi?id=23709

Adhemerval Zanella <adhemerval.zanella at linaro dot org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |adhemerval.zanella at linaro dot o
                   |                            |rg

--- Comment #20 from Adhemerval Zanella <adhemerval.zanella at linaro dot org> ---
The issue was introduced by commit 'Disable TSX on some Haswell processors.'
(2702856bf45c82cf8e69f2064f5aa15c0ceb6359) which change the some default flags
for unknown models.

Previously, new models were handled by the default switch option which assumed
a Core i3/i5/i7 if AVX is available. After the patch, Haswell models (0x3f,
0x3c, 0x45, 0x46) does not set the flags Fast_Rep_String, Fast_Unaligned_Load,
Fast_Unaligned_Copy, and Prefer_PMINUB_for_stringop for newer processors.

The most straightforward fix is to not mix the memory access flags set with
TSX, rather handle it on its own switch:

diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 122372862c..ecc82fc6af 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -297,7 +297,13 @@ init_cpu_features (struct cpu_features *cpu_features)
                    | bit_arch_Fast_Unaligned_Copy
                    | bit_arch_Prefer_PMINUB_for_stringop);
              break;
+           }

+        /* Disable TSX on some Haswell processors to avoid TSX on kernels that
+           weren't updated with the latest microcode package (which disables
+           broken feature by default).  */
+        switch (model)
+           {
            case 0x3f:
              /* Xeon E7 v3 with stepping >= 4 has working TSX.  */
              if (stepping >= 4)
azanella@birita:~/Projects/glibc/glibc-git-work$

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