Inquiry on AArch64 Simulator in GDB

[Andrew Dinn]

On 11/03/2024 11:31, Shiro B wrote:
> Thank you very much for your comprehensive response regarding the 
> AArch64 simulator. A userspace simulator is all I need, and this seems 
> will be very helpful to my project.

Glad to be able to help.

> During my exploration and testing, I believe I may have stumbled upon a 
> bug related to the UMINV instruction, as detailed in the ARM 
> documentation 
> (https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/UMINV--Unsigned-Minimum-across-Vector-?lang=en <https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/UMINV--Unsigned-Minimum-across-Vector-?lang=en>). According to ARM's specifications, it appears that after comparing and identifying the minimum value in a vector, the result should be stored in a floating-point/vector register, rather than a general-purpose register. The relevant code can be found here: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=sim/aarch64/simulator.c;h=1dde0b478c3d1bc9b88a63dd703225c9a2bb3703;hb=HEAD#l4482 <https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=sim/aarch64/simulator.c;h=1dde0b478c3d1bc9b88a63dd703225c9a2bb3703;hb=HEAD#l4482>
> 
> Admittedly, my familiarity with ARM64, especially SIMD instructions, is 
> not very extensive. However, through testing, I've noticed that the 
> simulation's outcome for this instruction indeed differs from that of an 
> actual CPU.
> 
> Could you please take a look at this observation and provide your 
> insights? I'm keen to understand whether this discrepancy could be 
> attributed to my limited understanding or if it indeed points to a 
> potential oversight in the simulator's implementation of the UMINV 
> instruction (and also UMAXV, SMINV, SMAXV).
> 
> Thank you once again for your invaluable feedback and for considering my 
> query. I look forward to your expert opinion on this matter.
Yes, I agree that is an error. The spec clearly states that all four 
instructions should place the result in the "SIMD&FP destination 
register encoded in the "Rd" field". Well done for spotting it.

regards,


Andrew Dinn
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