Fwd: [RFA] Fix for mcore simulator

Martin Simmons qqxnjvamvxwx@dyxyl.com
Tue Oct 10 21:35:40 GMT 2023

>>>>> On Thu, 5 Oct 2023 10:09:44 -0600, Jeff Law via Gdb said:
> Of course if the code is supposed to behave the same, then that points 
> to problems elsewhere (assembler, linker, simulator).  Sure enough the 
> mcore simulator was mis-handling the sign extension instructions.  The 
> simulator implementation of sextb is via paired shift-by-24 operations. 
> Similarly the simulator implements sexth via paired shift-by-16 operations.
> The temporary holding the value was declared as a "long" thus this 
> approach worked fine for hosts with a 32 bit wide long and failed 
> miserably for hosts with a 64 bit wide long.
> This patch makes the shift count automatically adjust based on the size 
> of the temporary.  It includes a simple test for sextb and sexth.  I 
> have _not_ done a full audit of the mcore simulator for more 32->64 bit 
> issues.

The use of long seems bogus to me.  Why not just declare tmp as int32_t?


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