How to get past ebreak instruction on RISC-V

[Jan Vrany]

Hi, 

I'm working on RISC-V compiler. To ease debugging of compiled code
I'm inserting `ebreak` instruction to interesting place (entry/exit
points or as a placeholder for unimplemented features). 

For example, the code might look like:

(gdb) disas 0x0000003FD6A36024, 0x0000003FD6A36048
Dump of assembler code from 0x3fd6a36024 to 0x3fd6a36048:
=> 0x0000003fd6a36024:  ebreak
   0x0000003fd6a36028:  sd      ra,-8(s11)
   0x0000003fd6a3602c:  addi    s11,s11,-16
   0x0000003fd6a36030:  ld      t3,80(s10)
   0x0000003fd6a36034:  addiw   a0,zero,42
   0x0000003fd6a36038:  addi    s11,s11,16
   0x0000003fd6a3603c:  ret
   0x0000003fd6a36040:  blt     s11,t3,0x3fd6a36000
   0x0000003fd6a36044:  ebreak
End of assembler dump.
(gdb) 

When compiled function is (attempted to) run, it stops on `ebreak` 
as expected: 

Thread 2 "main" received signal SIGTRAP, Trace/breakpoint trap.
[Switching to Thread 0x3ff7e681e0 (LWP 428777)]
0x0000003fd6a36024 in ?? ()

How can I get past the `ebreak` so I can `stepi` thought the following
instructions and debug? Thanks! 

Best, Jan