icache-dcache coherence on ARM
Xiaozhu Meng
mxz297@gmail.com
Mon May 6 19:30:00 GMT 2019
Hi,
I am reading gdb's source code to hopefully get answers for a question that
I have in my other project.
On ARM, the architecture does not guarantee that icache and dcache are
coherent. When GDB writes a software breakpoint into the inferior's address
space, is it possible that the inferior executes outdated code in icache
and thus miss the software breakpoint?
I try to search around the gdb code base to understand whether GDB flushes
icache or not, but could not find answers.
I appreciate any feedback!
Thanks,
--Xiaozhu
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