simulating non-standard memory regions

Mike Frysinger
Mon Feb 8 08:24:00 GMT 2010

the Blackfin processor follows a Harvard architecture, which means we have 
some memory regions that can only be executed (instruction) or read/write 
(data).  while the latter is no problem, the former isnt working out.  the 
sram region may not be accessed directly from the instruction set (i.e. via 
core load/stores), but it may be done via on-chip dma controllers.

the common simulator function sim_core_attach() has no problem creating an 
exec-only mapping, but the result isnt terribly useful since it cannot be read 
or written.  there doesnt seem to be a way to model this behavior.  it isnt a 
terribly big problem as it wont prevent correct code from being modeled 
correctly, but it doesnt catch incorrect code in the simulator.

another thing i'd like to do is model devices whose registers are memory 
mapped.  some registers may only be accessed via aligned 32bit or 16bit 
reads/writes.  is there a way to attach a memory map with custom read/write 
callback functions to handle these weird checks ?
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