Unifying the x86 FPU register sets

[Jim Blandy]

> 4) Several comments to Jim's message and the discussion that ensued:
> 
>   Jim> Since we're doing our own layout, we have the opportunity to set
>   Jim> aside the weird packing used by the FSAVE instruction, and have the
>   Jim> registers hold something more meaningful.  Thus, I've split out the
>   Jim> instruction segment selector and the opcode bits, previously
>   Jim> different bitfields of the $fcs register, into two separate
>   Jim> registers.
> 
> I think we need to discuss this a bit.  Please note that the FP
> registers are printed by GDB in two different ways: one is with the
> command "info float", the other with "info all-registers".  I agree
> that "info float" should present the information in a manner suitable
> for debugging numerical code, i.e., the opcode should be separated
> from the instruction selector, and its missing 5 bits should be added
> to the printed value; but I think that "info all-registers" should
> print the registers *exactly* as the CPU stores them.

I'm not sure what you mean, here.  Do you want "info all-registers" to
print the opcode and the FPU instruction pointer selector as a single
word?  Do you want to have a single GDB register which contains both
the opcode and FPU instruction pointer selector?

Why?