[Bug gdb/25318] New: Aarch64-SIM: BLR opcode does not support XLR register properly.

carlo_bramini at users dot sourceforge.net sourceware-bugzilla@sourceware.org
Thu Dec 26 13:10:00 GMT 2019


https://sourceware.org/bugzilla/show_bug.cgi?id=25318

            Bug ID: 25318
           Summary: Aarch64-SIM: BLR opcode does not support XLR register
                    properly.
           Product: gdb
           Version: HEAD
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: gdb
          Assignee: unassigned at sourceware dot org
          Reporter: carlo_bramini at users dot sourceforge.net
  Target Milestone: ---

Created attachment 12148
  --> https://sourceware.org/bugzilla/attachment.cgi?id=12148&action=edit
Extract from ARM A64 Instruction Set Architecture Manual.

I tried to debug my application with Aarch64 simulator of GDB, and I got a
crash. After some debugging, I discovered that the implementation of BLR opcode
is bugged because it does not support XLR register as parameter. Actually,
there are no restrictions to the register to be used, but the current code is
wrong because aarch64_save_LR() overwrites the address inside XLR before it can
be used with aarch64_set_next_PC().
I also attached a screenshot taken from the ARM A64 Instruction Set
Architecture manual which shows clearly that target address is acquired before
writing X[30].
Attached patch fixes this bug.
While compiling the Aarch64 simulator, I also got two little problems:
- in function ldrsw_abs() which is void but returning a value.
- function dexBranchImmediate() is also void, but used for returning a value.
Since they were extremely simple, I also included them into the attached patch.

Sincerely.

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