[PATCH 0/3] gdb/sim/riscv: Various big-endian fixes.

[Aleksa Paunovic]

This series fixes various issues for the big-endian RISC-V target. The
only major fix is keeping the instruction opcodes little-endian, as this
is what GCC does. 

Aleksa Paunovic (3):
  gdb/sim/riscv: Fix big-endian instruction fetch
  gdb/sim/riscv: Fix default endianness
  gdb/sim/riscv: Fix c-ext.s test on big-endian

 sim/riscv/interp.c              |  2 +-
 sim/riscv/sim-main.c            | 10 ++++++++--
 sim/testsuite/riscv/allinsn.exp |  2 +-
 sim/testsuite/riscv/c-ext.s     | 16 +++++++++++-----
 4 files changed, 21 insertions(+), 9 deletions(-)

-- 
2.43.0