[PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator

[Tsukasa OI]

Hi,

Due to opcodes changes (to add the 'Zmmul' extension in the
commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the
instruction simulator for RISC-V is now broken.

This is because only one side of my 'Zmmul' patchset is applied.

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/sim_riscv_zmmul>
Previous: 'Zmmul' v5:
<https://sourceware.org/pipermail/gdb-patches/2022-August/191295.html>


In the current master, multiply instructions of the RISC-V simulator doesn't
work.  The cause was simple.  The RISC-V simulator supports 'I', 'M' and 'A'
extensions and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to:

-   INSN_CLASS_ZMMUL (multiply instructions)
-   INSN_CLASS_M     (division instructions)

So, the simulator must handle INSN_CLASS_ZMMUL separately.

My 'Zmmul' patchset fixed that and I added a testcase (checks whether all
RV32M instructions run without any fault) but only opcodes part is applied
so it's now broken state for the simulator.

This is the simulator part of the original 'Zmmul' patchset (from PATCH v5).


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, all multiply instructions will still work.
Still, testing whether the simulator works with this extension
(with `make check-sim') requires it.


Thanks,
Tsukasa




Tsukasa OI (1):
  sim: Fix RISC-V multiply instructions on simulator

 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 803584b96d97e1f6ea50b0a0064d2a03ab0baa60
-- 
2.34.1