Fwd: Fix for v850e divq instruction
Jeff Law
jeffreyalaw@gmail.com
Mon Apr 4 22:49:00 GMT 2022
Similarly, this should have gone to the gdb list.
-------- Forwarded Message --------
Subject: Fix for v850e divq instruction
Date: Sun, 3 Apr 2022 10:25:16 -0600
From: Jeff Law <jeffreyalaw@gmail.com>
To: binutils@sourceware.org
This is the last of the correctness fixes I've been carrying around for
the v850.
Like the other recent fixes, this is another case where we haven't been
as careful as we should WRT host vs target types. For the divq
instruction both operands are 32 bit types. Yet in the simulator code
we convert them from unsigned int to signed long by assignment. So
0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the
result of our division.
The fix is simple, insert a cast to int32_t to force interpretation as a
signed value.
Testcase for the simulator is included. It has a trivial dependency on
the bins patch.
OK for the trunk?
JEff
-------------- next part --------------
diff --git a/sim/testsuite/v850/divq.cgs b/sim/testsuite/v850/divq.cgs
new file mode 100644
index 00000000000..8461f86f7a0
--- /dev/null
+++ b/sim/testsuite/v850/divq.cgs
@@ -0,0 +1,11 @@
+# v850 bins
+# mach: v850e3v5
+# as: -mv850e3v5
+
+ .include "testutils.inc"
+ seti 0xfffffffb r11
+ seti 0x32 r10
+ divq r11, r10, r11
+ reg r10, 0xfffffff6
+ reg r11, 0x0
+ pass
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index d2640577fc8..f90a0f7573c 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -3135,8 +3135,8 @@ v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, u
bfd_boolean overflow = FALSE;
/* Compute the result. */
- divide_by = op0;
- divide_this = op1;
+ divide_by = (int32_t)op0;
+ divide_this = (int32_t)op1;
if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
{
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