[PATCH 10/24] RISC-V sim: Fix ebreak.

[Jim Wilson]

From: Monk Chiang <monk@andestech.com>

Linux kernel no longer adds 4 to epc, and so gdb no longer subtracts 4,
so the simulator should no longer add 4 either.

	sim/riscv/
	* sim-main.c (execute_i): In case MATCH_SBREAK, don't increment
	pc in sim_engine_halt call.
---
 sim/riscv/sim-main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 48cf27f..710b67d 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1241,8 +1241,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_SBREAK:
       TRACE_INSN (cpu, "sbreak;");
-      /* GDB expects us to step over SBREAK.  */
-      sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP);
+      /* GDB expects us to stop at SBREAK.  */
+      sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_stopped, SIM_SIGTRAP);
       break;
     case MATCH_ECALL:
       TRACE_INSN (cpu, "ecall;");
-- 
2.7.4