[PATCH] Disable record btrace bts support for AMD processors

[Simon Marchi]

On 2020-05-14 2:54 p.m., Kevin Buettner via Gdb-patches wrote:
> Some Intel processors implement a Branch Trace Store (BTS) which GDB
> uses for reverse execution support via the "record btrace bts"
> command.
> 
> I have been unable to find a description of a similar feature in a
> recent (April 2020) AMD64 architecture reference:
> 
>     https://www.amd.com/system/files/TechDocs/40332.pdf
> 
> While it is the case that AMD processors have an LBR (last branch
> record) bit in the DebugCtl MSR, it seems that it affects only four
> MSRs when enabled.  The names of these MSRs are LastBranchToIP,
> LastBranchFromIP, LastIntToIP, and LastIntFromIP.  I can find no
> mention of anything more extensive.  While looking at an Intel
> architecture document, I noticed that Intel's P6 family from the
> mid-90s had registers of the same name.
> 
> Therefore...
> 
> This commit disables "btrace record bts" support in GDB for AMD

Do you mean "record btrace bts"?

> processors.

I'm curious, what happens right now when trying "record btrace bts"
on an AMD cpu?  And what happens after?  I could probably try myself,
but I think it would be a good thing to document here anyway.

Also, I suppose this affects "record btrace pt" too?

Simon