[PING] [PATCH] RISC-V: Update CSR to privileged spec 1.11.
Nelson Chu
nelson.chu@sifive.com
Tue Mar 24 05:05:32 GMT 2020
Hi gdb,
PING :)
Thanks
Nelson
On Thu, Mar 12, 2020 at 6:01 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> gas/
> * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
> * testsuite/gas/riscv/alias-csr.s: Likewise.
> * testsuite/gas/riscv/no-aliases-csr.d: Move this
> to priv-reg-pseudo-noalias.
> * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
> * testsuite/gas/riscv/bad-csr.l: Likewise.
> * testsuite/gas/riscv/bad-csr.s: Likewise.
> * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
> * testsuite/gas/riscv/satp.s: Likewise.
> * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
> csr instruction, including alias-csr testcase.
> * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
> * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
> pseudo instruction with objdump -Mno-aliases.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
> * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
> * testsuite/gas/riscv/priv-reg.s: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
>
> include/
> * opcode/riscv-opc.h: Update CSR to 1.11.
>
> gdb/
> * features/riscv/32bit-csr.xml: Regenerated.
> * features/riscv/64bit-csr.xml: Regenerated.
> ---
> gas/testsuite/gas/riscv/alias-csr.d | 23 -
> gas/testsuite/gas/riscv/alias-csr.s | 14 -
> gas/testsuite/gas/riscv/bad-csr.d | 3 -
> gas/testsuite/gas/riscv/bad-csr.l | 2 -
> gas/testsuite/gas/riscv/bad-csr.s | 1 -
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 7 +-
> gas/testsuite/gas/riscv/csr-dw-regnums.s | 9 +-
> gas/testsuite/gas/riscv/no-aliases-csr.d | 23 -
> .../gas/riscv/priv-reg-fail-nonexistent.d | 3 +
> .../gas/riscv/priv-reg-fail-nonexistent.l | 2 +
> .../gas/riscv/priv-reg-fail-nonexistent.s | 1 +
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 4 +-
> gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d | 36 ++
> gas/testsuite/gas/riscv/priv-reg-pseudo.d | 36 ++
> gas/testsuite/gas/riscv/priv-reg-pseudo.s | 33 ++
> gas/testsuite/gas/riscv/priv-reg.d | 491 +++++++++++----------
> gas/testsuite/gas/riscv/priv-reg.s | 114 ++---
> gas/testsuite/gas/riscv/satp.d | 11 -
> gas/testsuite/gas/riscv/satp.s | 3 -
> gdb/features/riscv/32bit-csr.xml | 5 +-
> gdb/features/riscv/64bit-csr.xml | 5 +-
> include/opcode/riscv-opc.h | 25 +-
> 22 files changed, 454 insertions(+), 397 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/alias-csr.d
> delete mode 100644 gas/testsuite/gas/riscv/alias-csr.s
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
> delete mode 100644 gas/testsuite/gas/riscv/no-aliases-csr.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.s
> delete mode 100644 gas/testsuite/gas/riscv/satp.d
> delete mode 100644 gas/testsuite/gas/riscv/satp.s
>
> diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
> deleted file mode 100644
> index af5c591..0000000
> --- a/gas/testsuite/gas/riscv/alias-csr.d
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#source: alias-csr.s
> -#as: -march=rv64if
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <alias_csr>:
> -[ ]+0:[ ]+003022f3[ ]+frcsr[ ]+t0
> -[ ]+4:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> -[ ]+8:[ ]+00339073[ ]+fscsr[ ]+t2
> -[ ]+c:[ ]+002022f3[ ]+frrm[ ]+t0
> -[ ]+10:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> -[ ]+14:[ ]+00231073[ ]+fsrm[ ]+t1
> -[ ]+18:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> -[ ]+1c:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> -[ ]+20:[ ]+001022f3[ ]+frflags[ ]+t0
> -[ ]+24:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> -[ ]+28:[ ]+00131073[ ]+fsflags[ ]+t1
> -[ ]+2c:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> -[ ]+30:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
> deleted file mode 100644
> index 8577de1..0000000
> --- a/gas/testsuite/gas/riscv/alias-csr.s
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -alias_csr:
> - frcsr t0
> - fscsr t0, t2
> - fscsr t2
> - frrm t0
> - fsrm t0, t1
> - fsrm t1
> - fsrmi t0, 31
> - fsrmi 31
> - frflags t0
> - fsflags t0, t1
> - fsflags t1
> - fsflagsi t0, 31
> - fsflagsi 31
> diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
> deleted file mode 100644
> index 6863123..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as:
> -#source: bad-csr.s
> -#error_output: bad-csr.l
> diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
> deleted file mode 100644
> index a0bb8a6..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
> deleted file mode 100644
> index 6e6d27e..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.s
> +++ /dev/null
> @@ -1 +0,0 @@
> - csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> index a7b415e..df9642f 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> @@ -202,6 +202,7 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
> DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
> DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
> DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
> DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
> @@ -237,7 +238,8 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
> DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
> DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
> - DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> + DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
> DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
> DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
> DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
> @@ -254,12 +256,13 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
> DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
> DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
> - DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
> DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
> DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
> DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
> DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
> DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
> DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> DW_CFA_nop
> #...
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> index b29e9da..4101a41 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> @@ -192,6 +192,7 @@ _start:
> .cfi_offset mhpmcounter29h, 11892
> .cfi_offset mhpmcounter30h, 11896
> .cfi_offset mhpmcounter31h, 11900
> + .cfi_offset mcountinhibit, 3200
> .cfi_offset mhpmevent3, 3212
> .cfi_offset mhpmevent4, 3216
> .cfi_offset mhpmevent5, 3220
> @@ -227,7 +228,10 @@ _start:
> .cfi_offset tdata3, 7820
> .cfi_offset dcsr, 7872
> .cfi_offset dpc, 7876
> - .cfi_offset dscratch, 7880
> + .cfi_offset dscratch0, 7880
> + .cfi_offset dscratch1, 7884
> +
> + # dropped in the current 1.11 priv spec.
> .cfi_offset hstatus, 2048
> .cfi_offset hedeleg, 2056
> .cfi_offset hideleg, 2060
> @@ -244,12 +248,13 @@ _start:
> .cfi_offset mibound, 3596
> .cfi_offset mdbase, 3600
> .cfi_offset mdbound, 3604
> - .cfi_offset mucounteren, 3200
> .cfi_offset mscounteren, 3204
> .cfi_offset mhcounteren, 3208
> .cfi_offset ubadaddr, 268
> .cfi_offset sbadaddr, 1292
> .cfi_offset sptbr, 1536
> .cfi_offset mbadaddr, 3340
> + .cfi_offset mucounteren, 3200
> + .cfi_offset dscratch, 7880
> nop
> .cfi_endproc
> diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
> deleted file mode 100644
> index 2275330..0000000
> --- a/gas/testsuite/gas/riscv/no-aliases-csr.d
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#source: alias-csr.s
> -#as: -march=rv64if
> -#objdump: -dr -Mno-aliases
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <alias_csr>:
> -[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> -[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> -[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> -[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> -[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> -[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> -[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> -[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> -[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> -[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> -[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> -[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> -[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> new file mode 100644
> index 0000000..9bb3f82
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> @@ -0,0 +1,3 @@
> +#as:
> +#source: priv-reg-fail-nonexistent.s
> +#error_output: priv-reg-fail-nonexistent.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> new file mode 100644
> index 0000000..a0bb8a6
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> @@ -0,0 +1,2 @@
> +.*: Assembler messages:
> +.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> new file mode 100644
> index 0000000..6e6d27e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> @@ -0,0 +1 @@
> + csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> index 9123672..fa5a1b4 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> @@ -31,6 +31,8 @@
> .*Warning: Invalid CSR `hpmcounter29h' for the current ISA
> .*Warning: Invalid CSR `hpmcounter30h' for the current ISA
> .*Warning: Invalid CSR `hpmcounter31h' for the current ISA
> +.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> +.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> .*Warning: Invalid CSR `mcycleh' for the current ISA
> .*Warning: Invalid CSR `minstreth' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter3h' for the current ISA
> @@ -62,5 +64,3 @@
> .*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
> -.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> -.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> new file mode 100644
> index 0000000..e0acb18
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> @@ -0,0 +1,36 @@
> +#source: priv-reg-pseudo.s
> +#as: -march=rv32if
> +#objdump: -dr -Mno-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <pseudo_csr_insn>:
> +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrrs[ ]+t0,ustatus,zero
> +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrrw[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrrs[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrrc[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrrwi[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrrsi[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrrci[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+csrrs[ ]+t0,cycle,zero
> +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+csrrs[ ]+t0,time,zero
> +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+csrrs[ ]+t0,instret,zero
> +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+csrrs[ ]+t0,cycleh,zero
> +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+csrrs[ ]+t0,timeh,zero
> +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+csrrs[ ]+t0,instreth,zero
> +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> +[ ]+[0-9a-f]+:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> +[ ]+[0-9a-f]+:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> +[ ]+[0-9a-f]+:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.d b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> new file mode 100644
> index 0000000..4243510
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> @@ -0,0 +1,36 @@
> +#source: priv-reg-pseudo.s
> +#as: -march=rv32if
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <pseudo_csr_insn>:
> +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrr[ ]+t0,ustatus
> +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrw[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrs[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrc[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrwi[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrsi[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrci[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+rdcycle[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+rdtime[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+rdinstret[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+rdcycleh[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+rdtimeh[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+rdinstreth[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+frcsr[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> +[ ]+[0-9a-f]+:[ ]+00339073[ ]+fscsr[ ]+t2
> +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+frrm[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> +[ ]+[0-9a-f]+:[ ]+00231073[ ]+fsrm[ ]+t1
> +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+frflags[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> +[ ]+[0-9a-f]+:[ ]+00131073[ ]+fsflags[ ]+t1
> +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.s b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> new file mode 100644
> index 0000000..8efaa4e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> @@ -0,0 +1,33 @@
> +pseudo_csr_insn:
> + # i-ext
> + csrr t0, 0x0
> + csrw 0x0, t0
> + csrs 0x0, t0
> + csrc 0x0, t0
> + csrwi 0x0, 31
> + csrsi 0x0, 31
> + csrci 0x0, 31
> +
> + rdcycle t0
> + rdtime t0
> + rdinstret t0
> +
> + # rv32i-ext
> + rdcycleh t0
> + rdtimeh t0
> + rdinstreth t0
> +
> + # f-ext
> + frcsr t0 # frsr
> + fscsr t0, t2 # fssr
> + fscsr t2 # fssr
> + frrm t0
> + fsrm t0, t1
> + fsrm t1
> + fsrmi t0, 31
> + fsrmi 31
> + frflags t0
> + fsflags t0, t1
> + fsflags t1
> + fsflagsi t0, 31
> + fsflagsi 31
> diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> index 8b7a7bf..8fc41d2 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.d
> +++ b/gas/testsuite/gas/riscv/priv-reg.d
> @@ -7,247 +7,250 @@
> Disassembly of section .text:
>
> 0+000 <.text>:
> -[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> -[ ]+4:[ ]+00402573[ ]+csrr[ ]+a0,uie
> -[ ]+8:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> -[ ]+c:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> -[ ]+10:[ ]+04102573[ ]+csrr[ ]+a0,uepc
> -[ ]+14:[ ]+04202573[ ]+csrr[ ]+a0,ucause
> -[ ]+18:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
> -[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
> -[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
> -[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
> -[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
> -[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
> -[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
> -[ ]+38:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> -[ ]+3c:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> -[ ]+40:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> -[ ]+44:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> -[ ]+48:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> -[ ]+4c:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> -[ ]+50:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> -[ ]+54:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> -[ ]+58:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> -[ ]+5c:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> -[ ]+60:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> -[ ]+64:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> -[ ]+68:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> -[ ]+6c:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> -[ ]+70:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> -[ ]+74:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
> -[ ]+78:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
> -[ ]+7c:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
> -[ ]+80:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
> -[ ]+84:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
> -[ ]+88:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
> -[ ]+8c:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
> -[ ]+90:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
> -[ ]+94:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
> -[ ]+98:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
> -[ ]+9c:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
> -[ ]+a0:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
> -[ ]+a4:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
> -[ ]+a8:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
> -[ ]+ac:[ ]+c8002573[ ]+rdcycleh[ ]+a0
> -[ ]+b0:[ ]+c8102573[ ]+rdtimeh[ ]+a0
> -[ ]+b4:[ ]+c8202573[ ]+rdinstreth[ ]+a0
> -[ ]+b8:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
> -[ ]+bc:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
> -[ ]+c0:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
> -[ ]+c4:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
> -[ ]+c8:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
> -[ ]+cc:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
> -[ ]+d0:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
> -[ ]+d4:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
> -[ ]+d8:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
> -[ ]+dc:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
> -[ ]+e0:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
> -[ ]+e4:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
> -[ ]+e8:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
> -[ ]+ec:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
> -[ ]+f0:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
> -[ ]+f4:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
> -[ ]+f8:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
> -[ ]+fc:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
> -[ ]+100:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
> -[ ]+104:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
> -[ ]+108:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
> -[ ]+10c:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
> -[ ]+110:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
> -[ ]+114:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
> -[ ]+118:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
> -[ ]+11c:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
> -[ ]+120:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
> -[ ]+124:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
> -[ ]+128:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
> -[ ]+12c:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
> -[ ]+130:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
> -[ ]+134:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
> -[ ]+138:[ ]+10402573[ ]+csrr[ ]+a0,sie
> -[ ]+13c:[ ]+10502573[ ]+csrr[ ]+a0,stvec
> -[ ]+140:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
> -[ ]+144:[ ]+14102573[ ]+csrr[ ]+a0,sepc
> -[ ]+148:[ ]+14202573[ ]+csrr[ ]+a0,scause
> -[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,stval
> -[ ]+150:[ ]+14402573[ ]+csrr[ ]+a0,sip
> -[ ]+154:[ ]+18002573[ ]+csrr[ ]+a0,satp
> -[ ]+158:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> -[ ]+15c:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> -[ ]+160:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> -[ ]+164:[ ]+20402573[ ]+csrr[ ]+a0,hie
> -[ ]+168:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> -[ ]+16c:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> -[ ]+170:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> -[ ]+174:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> -[ ]+178:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> -[ ]+17c:[ ]+24402573[ ]+csrr[ ]+a0,hip
> -[ ]+180:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
> -[ ]+184:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
> -[ ]+188:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
> -[ ]+18c:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
> -[ ]+190:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
> -[ ]+194:[ ]+30102573[ ]+csrr[ ]+a0,misa
> -[ ]+198:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
> -[ ]+19c:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
> -[ ]+1a0:[ ]+30402573[ ]+csrr[ ]+a0,mie
> -[ ]+1a4:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
> -[ ]+1a8:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
> -[ ]+1ac:[ ]+34102573[ ]+csrr[ ]+a0,mepc
> -[ ]+1b0:[ ]+34202573[ ]+csrr[ ]+a0,mcause
> -[ ]+1b4:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> -[ ]+1b8:[ ]+34402573[ ]+csrr[ ]+a0,mip
> -[ ]+1bc:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> -[ ]+1c0:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> -[ ]+1c4:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> -[ ]+1c8:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> -[ ]+1cc:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> -[ ]+1d0:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> -[ ]+1d4:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> -[ ]+1d8:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> -[ ]+1dc:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> -[ ]+1e0:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> -[ ]+1e4:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> -[ ]+1e8:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> -[ ]+1ec:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> -[ ]+1f0:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> -[ ]+1f4:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> -[ ]+1f8:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> -[ ]+1fc:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> -[ ]+200:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> -[ ]+204:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> -[ ]+208:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> -[ ]+20c:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> -[ ]+210:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> -[ ]+214:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> -[ ]+218:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> -[ ]+21c:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> -[ ]+220:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> -[ ]+224:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> -[ ]+228:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> -[ ]+22c:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> -[ ]+230:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> -[ ]+234:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> -[ ]+238:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> -[ ]+23c:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> -[ ]+240:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> -[ ]+244:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> -[ ]+248:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> -[ ]+24c:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> -[ ]+250:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> -[ ]+254:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> -[ ]+258:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> -[ ]+25c:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> -[ ]+260:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> -[ ]+264:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> -[ ]+268:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> -[ ]+26c:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> -[ ]+270:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> -[ ]+274:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> -[ ]+278:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> -[ ]+27c:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> -[ ]+280:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> -[ ]+284:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> -[ ]+288:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> -[ ]+28c:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> -[ ]+290:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> -[ ]+294:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> -[ ]+298:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> -[ ]+29c:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> -[ ]+2a0:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> -[ ]+2a4:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> -[ ]+2a8:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> -[ ]+2ac:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> -[ ]+2b0:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> -[ ]+2b4:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> -[ ]+2b8:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> -[ ]+2bc:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> -[ ]+2c0:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> -[ ]+2c4:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> -[ ]+2c8:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> -[ ]+2cc:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
> -[ ]+2d0:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> -[ ]+2d4:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> -[ ]+2d8:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> -[ ]+2dc:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> -[ ]+2e0:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> -[ ]+2e4:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> -[ ]+2e8:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> -[ ]+2ec:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> -[ ]+2f0:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> -[ ]+2f4:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> -[ ]+2f8:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> -[ ]+2fc:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> -[ ]+300:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> -[ ]+304:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> -[ ]+308:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> -[ ]+30c:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> -[ ]+310:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> -[ ]+314:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> -[ ]+318:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> -[ ]+31c:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> -[ ]+320:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> -[ ]+324:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> -[ ]+328:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> -[ ]+32c:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> -[ ]+330:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> -[ ]+334:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> -[ ]+338:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> -[ ]+33c:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> -[ ]+340:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> -[ ]+344:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> -[ ]+348:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> -[ ]+34c:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> -[ ]+350:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> -[ ]+354:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> -[ ]+358:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> -[ ]+35c:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> -[ ]+360:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> -[ ]+364:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
> -[ ]+368:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+36c:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
> -[ ]+370:[ ]+14302573[ ]+csrr[ ]+a0,stval
> -[ ]+374:[ ]+18002573[ ]+csrr[ ]+a0,satp
> -[ ]+378:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
> -[ ]+37c:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> -[ ]+380:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> -[ ]+384:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> -[ ]+388:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
> -[ ]+38c:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
> -[ ]+390:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
> -[ ]+394:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
> -[ ]+398:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
> -[ ]+39c:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
> -[ ]+3a0:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
> -[ ]+3a4:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
> -[ ]+3a8:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
> -[ ]+3ac:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
> -[ ]+3b0:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
> -[ ]+3b4:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> -[ ]+3b8:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> -[ ]+3bc:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> -[ ]+3c0:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> -[ ]+3c4:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> -[ ]+3c8:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
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> +[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> +[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> +[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> +[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
> +[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
> +[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> +[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> +[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> +[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> +[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> +[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
> +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
> +[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> +[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> +[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> +[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> +[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> +[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> +[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> +[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
> index 72d97f9..8353f70 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.s
> +++ b/gas/testsuite/gas/riscv/priv-reg.s
> @@ -1,7 +1,8 @@
> .macro csr val
> csrr a0,\val
> .endm
> -# 1.9.1 registers
> +
> + # Supported the current priv spec 1.11.
> csr ustatus
> csr uie
> csr utvec
> @@ -9,7 +10,7 @@
> csr uscratch
> csr uepc
> csr ucause
> - csr ubadaddr
> + csr utval # Added in 1.10
> csr uip
>
> csr fflags
> @@ -86,26 +87,15 @@
> csr sideleg
> csr sie
> csr stvec
> + csr scounteren # Added in 1.10
>
> csr sscratch
> csr sepc
> csr scause
> - csr sbadaddr
> + csr stval # Added in 1.10
> csr sip
>
> - csr sptbr
> -
> - csr hstatus
> - csr hedeleg
> - csr hideleg
> - csr hie
> - csr htvec
> -
> - csr hscratch
> - csr hepc
> - csr hcause
> - csr hbadaddr
> - csr hip
> + csr satp # Added in 1.10
>
> csr mvendorid
> csr marchid
> @@ -113,24 +103,39 @@
> csr mhartid
>
> csr mstatus
> - csr misa
> + csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
> csr medeleg
> csr mideleg
> csr mie
> csr mtvec
> + csr mcounteren # Added in 1.10
>
> csr mscratch
> csr mepc
> csr mcause
> - csr mbadaddr
> + csr mtval # Added in 1.10
> csr mip
>
> - csr mbase
> - csr mbound
> - csr mibase
> - csr mibound
> - csr mdbase
> - csr mdbound
> + csr pmpcfg0 # Added in 1.10
> + csr pmpcfg1 # Added in 1.10
> + csr pmpcfg2 # Added in 1.10
> + csr pmpcfg3 # Added in 1.10
> + csr pmpaddr0 # Added in 1.10
> + csr pmpaddr1 # Added in 1.10
> + csr pmpaddr2 # Added in 1.10
> + csr pmpaddr3 # Added in 1.10
> + csr pmpaddr4 # Added in 1.10
> + csr pmpaddr5 # Added in 1.10
> + csr pmpaddr6 # Added in 1.10
> + csr pmpaddr7 # Added in 1.10
> + csr pmpaddr8 # Added in 1.10
> + csr pmpaddr9 # Added in 1.10
> + csr pmpaddr10 # Added in 1.10
> + csr pmpaddr11 # Added in 1.10
> + csr pmpaddr12 # Added in 1.10
> + csr pmpaddr13 # Added in 1.10
> + csr pmpaddr14 # Added in 1.10
> + csr pmpaddr15 # Added in 1.10
>
> csr mcycle
> csr minstret
> @@ -195,10 +200,7 @@
> csr mhpmcounter30h
> csr mhpmcounter31h
>
> - csr mucounteren
> - csr mscounteren
> - csr mhcounteren
> -
> + csr mcountinhibit # Added in 1.11
> csr mhpmevent3
> csr mhpmevent4
> csr mhpmevent5
> @@ -236,34 +238,32 @@
>
> csr dcsr
> csr dpc
> - csr dscratch
> -# 1.10 registers
> - csr utval
> -
> - csr scounteren
> - csr stval
> - csr satp
> + csr dscratch0 # Added in 1.11
> + csr dscratch1 # Added in 1.11
>
> - csr mcounteren
> - csr mtval
> + # Supported in previous priv spec, but dropped now.
> + csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
> + csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
> + csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
> + csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
> + csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
> + csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
>
> - csr pmpcfg0
> - csr pmpcfg1
> - csr pmpcfg2
> - csr pmpcfg3
> - csr pmpaddr0
> - csr pmpaddr1
> - csr pmpaddr2
> - csr pmpaddr3
> - csr pmpaddr4
> - csr pmpaddr5
> - csr pmpaddr6
> - csr pmpaddr7
> - csr pmpaddr8
> - csr pmpaddr9
> - csr pmpaddr10
> - csr pmpaddr11
> - csr pmpaddr12
> - csr pmpaddr13
> - csr pmpaddr14
> - csr pmpaddr15
> + csr hstatus # 0x200, dropped in 1.10
> + csr hedeleg # 0x202, dropped in 1.10
> + csr hideleg # 0x203, dropped in 1.10
> + csr hie # 0x204, dropped in 1.10
> + csr htvec # 0x205, dropped in 1.10
> + csr hscratch # 0x240, dropped in 1.10
> + csr hepc # 0x241, dropped in 1.10
> + csr hcause # 0x242, dropped in 1.10
> + csr hbadaddr # 0x243, dropped in 1.10
> + csr hip # 0x244, dropped in 1.10
> + csr mbase # 0x380, dropped in 1.10
> + csr mbound # 0x381, dropped in 1.10
> + csr mibase # 0x382, dropped in 1.10
> + csr mibound # 0x383, dropped in 1.10
> + csr mdbase # 0x384, dropped in 1.10
> + csr mdbound # 0x385, dropped in 1.10
> + csr mscounteren # 0x321, dropped in 1.10
> + csr mhcounteren # 0x322, dropped in 1.10
> diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
> deleted file mode 100644
> index 823601c..0000000
> --- a/gas/testsuite/gas/riscv/satp.d
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -#as:
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> -[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
> deleted file mode 100644
> index f8aa766..0000000
> --- a/gas/testsuite/gas/riscv/satp.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - csrr t0, satp
> - csrr t0, sptbr
> diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
> index 5b79499..8173eeb 100644
> --- a/gdb/features/riscv/32bit-csr.xml
> +++ b/gdb/features/riscv/32bit-csr.xml
> @@ -192,6 +192,7 @@
> <reg name="mhpmcounter29h" bitsize="32"/>
> <reg name="mhpmcounter30h" bitsize="32"/>
> <reg name="mhpmcounter31h" bitsize="32"/>
> + <reg name="mcountinhibit" bitsize="32"/>
> <reg name="mhpmevent3" bitsize="32"/>
> <reg name="mhpmevent4" bitsize="32"/>
> <reg name="mhpmevent5" bitsize="32"/>
> @@ -227,7 +228,8 @@
> <reg name="tdata3" bitsize="32"/>
> <reg name="dcsr" bitsize="32"/>
> <reg name="dpc" bitsize="32"/>
> - <reg name="dscratch" bitsize="32"/>
> + <reg name="dscratch0" bitsize="32"/>
> + <reg name="dscratch1" bitsize="32"/>
> <reg name="hstatus" bitsize="32"/>
> <reg name="hedeleg" bitsize="32"/>
> <reg name="hideleg" bitsize="32"/>
> @@ -244,7 +246,6 @@
> <reg name="mibound" bitsize="32"/>
> <reg name="mdbase" bitsize="32"/>
> <reg name="mdbound" bitsize="32"/>
> - <reg name="mucounteren" bitsize="32"/>
> <reg name="mscounteren" bitsize="32"/>
> <reg name="mhcounteren" bitsize="32"/>
> </feature>
> diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
> index 8ec0ffe..ed28964 100644
> --- a/gdb/features/riscv/64bit-csr.xml
> +++ b/gdb/features/riscv/64bit-csr.xml
> @@ -127,6 +127,7 @@
> <reg name="mhpmcounter29" bitsize="64"/>
> <reg name="mhpmcounter30" bitsize="64"/>
> <reg name="mhpmcounter31" bitsize="64"/>
> + <reg name="mcountinhibit" bitsize="64"/>
> <reg name="mhpmevent3" bitsize="64"/>
> <reg name="mhpmevent4" bitsize="64"/>
> <reg name="mhpmevent5" bitsize="64"/>
> @@ -162,7 +163,8 @@
> <reg name="tdata3" bitsize="64"/>
> <reg name="dcsr" bitsize="64"/>
> <reg name="dpc" bitsize="64"/>
> - <reg name="dscratch" bitsize="64"/>
> + <reg name="dscratch0" bitsize="64"/>
> + <reg name="dscratch1" bitsize="64"/>
> <reg name="hstatus" bitsize="64"/>
> <reg name="hedeleg" bitsize="64"/>
> <reg name="hideleg" bitsize="64"/>
> @@ -179,7 +181,6 @@
> <reg name="mibound" bitsize="64"/>
> <reg name="mdbase" bitsize="64"/>
> <reg name="mdbound" bitsize="64"/>
> - <reg name="mucounteren" bitsize="64"/>
> <reg name="mscounteren" bitsize="64"/>
> <reg name="mhcounteren" bitsize="64"/>
> </feature>
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 18d0b15..fe00bb6 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -575,6 +575,7 @@
> #define MASK_CUSTOM3_RD_RS1 0x707f
> #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
> #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
> +/* Support CSR to priv spec 1.11. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> #define CSR_UTVEC 0x5
> @@ -655,6 +656,7 @@
> #define CSR_SIDELEG 0x103
> #define CSR_SIE 0x104
> #define CSR_STVEC 0x105
> +/* scounteren is present int priv spec 1.10. */
> #define CSR_SCOUNTEREN 0x106
> #define CSR_SSCRATCH 0x140
> #define CSR_SEPC 0x141
> @@ -667,17 +669,20 @@
> #define CSR_MIMPID 0xf13
> #define CSR_MHARTID 0xf14
> #define CSR_MSTATUS 0x300
> +/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MISA 0x301
> #define CSR_MEDELEG 0x302
> #define CSR_MIDELEG 0x303
> #define CSR_MIE 0x304
> #define CSR_MTVEC 0x305
> +/* mcounteren is present in priv spec 1.10. */
> #define CSR_MCOUNTEREN 0x306
> #define CSR_MSCRATCH 0x340
> #define CSR_MEPC 0x341
> #define CSR_MCAUSE 0x342
> #define CSR_MTVAL 0x343
> #define CSR_MIP 0x344
> +/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
> #define CSR_PMPCFG0 0x3a0
> #define CSR_PMPCFG1 0x3a1
> #define CSR_PMPCFG2 0x3a2
> @@ -760,6 +765,8 @@
> #define CSR_MHPMCOUNTER29H 0xb9d
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
> +/* mcountinhibit is present in priv spec 1.11. */
> +#define CSR_MCOUNTINHIBIT 0x320
> #define CSR_MHPMEVENT3 0x323
> #define CSR_MHPMEVENT4 0x324
> #define CSR_MHPMEVENT5 0x325
> @@ -795,8 +802,10 @@
> #define CSR_TDATA3 0x7a3
> #define CSR_DCSR 0x7b0
> #define CSR_DPC 0x7b1
> -#define CSR_DSCRATCH 0x7b2
> -/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> +/* dscratch0 and dscratch1 are present in priv spec 1.11. */
> +#define CSR_DSCRATCH0 0x7b2
> +#define CSR_DSCRATCH1 0x7b3
> +/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
> #define CSR_HSTATUS 0x200
> #define CSR_HEDELEG 0x202
> #define CSR_HIDELEG 0x203
> @@ -807,16 +816,15 @@
> #define CSR_HCAUSE 0x242
> #define CSR_HBADADDR 0x243
> #define CSR_HIP 0x244
> -/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MBASE 0x380
> #define CSR_MBOUND 0x381
> #define CSR_MIBASE 0x382
> #define CSR_MIBOUND 0x383
> #define CSR_MDBASE 0x384
> #define CSR_MDBOUND 0x385
> -#define CSR_MUCOUNTEREN 0x320
> #define CSR_MSCOUNTEREN 0x321
> #define CSR_MHCOUNTEREN 0x322
> +
> #define CAUSE_MISALIGNED_FETCH 0x0
> #define CAUSE_FAULT_FETCH 0x1
> #define CAUSE_ILLEGAL_INSTRUCTION 0x2
> @@ -1301,6 +1309,7 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
> +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
> @@ -1336,7 +1345,8 @@ DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
> DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
> DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
> DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
> -DECLARE_CSR(dscratch, CSR_DSCRATCH, CSR_CLASS_I)
> +DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
> +DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
> /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
> DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
> @@ -1354,7 +1364,6 @@ DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
> DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
> DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
> DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
> -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN, CSR_CLASS_I)
> DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
> DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
> #endif
> @@ -1367,6 +1376,10 @@ DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
> DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
> /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
> DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
> +/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
> +DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> +/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
> +DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
> #endif
> #ifdef DECLARE_CAUSE
> DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
> --
> 2.7.4
>
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