[PATCH 0/8] RISC-V target description and register handling fixes

[Nelson Chu]

Hi Andrew,

These are great!  Thank you, Jim and Tom very much.  You make the CSR
support more sense now.  The code seems to be changed dramatically.  I
will spend time to figure them out, and then see what needs to be
modified in binutils, including my recent patch to support the missing
debug CSR.

Thanks
Nelson

On Wed, Jun 17, 2020 at 1:14 AM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
>
> This series includes a mixed bag of changes around RISC-V's target
> description and general register handling.  This includes a fix for an
> issue Tom reported here:
>
>   https://sourceware.org/pipermail/gdb-patches/2020-June/169323.html
>
> Though most of the changes are RISC-V only, patch #6 does make a
> change to the generic target description handling code so is probably
> worth additional review.
>
> Feedback welcome,
>
> Thanks,
> Andrew
>
> ---
>
> Andrew Burgess (8):
>   gdb/riscv: Improved register alias name creation
>   gdb/riscv: Fix whitespace error
>   gdb/riscv: Take CSR names from target description
>   gdb/riscv: Remove CSR feature file
>   gdb/riscv: Improve support for matching against target descriptions
>   gdb: Extend target description processing of unknown registers
>   gdb/riscv: Record information about unknown tdesc registers
>   gdb/riscv: Loop over all registers for 'info all-registers'