[PATCH] RISC-V: enable have_nonsteppable_watchpoint by default

[Pedro Alves]

-- 
Thanks,
Pedro Alves
On 10/09/2018 06:29 PM, Paul Koning wrote:
> 
> 
>> On Oct 9, 2018, at 1:20 PM, Craig Blackmore <craig.blackmore@embecosm.com> wrote:
>>
>>
>>
>> On 08/10/18 15:51, Joel Brobecker wrote:
>>>>> I think MIPS is one.  The documentation is not entirely clear but
>>>>> that's what I remember from using it.
>>>> x86 is another.  But my question is -- do we know of any RISC-V
>>>> implementation that triggers after the write, given that the spec
>>>> says it should trigger before the write.
>> I don't know of any RISC-V implementations that trigger after the write.
>> The debug spec has 'suggested breakpoint timings' but the triggers are
>> allowed to fire at whatever point is most convenient for the implementation.
> 
> I missed that the question was specific to RISC-V.
> 
> If the spec says that timing is up to the implementation, that seems to mean GDB can't rely on the break occurring before the write -- the fact that current implementations do so isn't sufficient if later implementation are allowed to differ.
> 
> I assume GDB cares which it is, which suggests that the implementation has to tell GDB which flavor of write watchpoint it has.

Yes, which is what I had suggested earlier in the thread.  But the
thing is, no one knows about any implementation that doesn't
trap before the write.  Does the "point is most convenient"
include a few instructions/cycles after the write (more than
one insn?).  Because, there are archs like that (some ARM
variants, IIRC).  If so, before/after will not be sufficient.
Thus, I still think we should go with the simple approach until
we learn about some real implementation that needs something else.

Thanks,
Pedro Alves