[PATCHv4 2/2] gdb: Initial baremetal riscv support
Yao Qi
qiyaoltc@gmail.com
Tue Mar 6 11:35:00 GMT 2018
Andrew Burgess <andrew.burgess@embecosm.com> writes:
> +/* Read the MISA register from the target. The register will only be read
> + once, and the value read will be cached. If the register can't be read
> + from the target then a default value (0) will be returned. If the
I don't understand the rationale that we maintain MISA register in a
per-inferior data. Why don't we put it into regcache? I know MISA
won't change, but it makes few sense to me to maintain register out of
regcache.
> + pointer READ_P is not null, then the bool pointed to is updated to
> + indicate if the value returned was read from the target (true) or is the
> + default (false). */
> +
> +static uint32_t
> +riscv_read_misa_reg (bool *read_p)
> +{
> + struct riscv_inferior_data *inf_data
> + = riscv_inferior_data (current_inferior ());
> +
> + if (!inf_data->misa_read && target_has_registers)
> + {
> + uint32_t value = 0;
> + struct frame_info *frame = get_current_frame ();
> +
> + TRY
> + {
> + value = get_frame_register_unsigned (frame, RISCV_CSR_MISA_REGNUM);
> + }
> + CATCH (ex, RETURN_MASK_ERROR)
> + {
> + /* Old cores might have MISA located at a different offset. */
> + value = get_frame_register_unsigned (frame,
> + RISCV_CSR_LEGACY_MISA_REGNUM);
> + }
> + END_CATCH
> +
> + inf_data->misa_read = true;
> + inf_data->misa_value = value;
> + }
> +
> + if (read_p != nullptr)
> + *read_p = inf_data->misa_read;
> +
> + return inf_data->misa_value;
> +}
--
Yao (齐尧)
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