[PATCH] aarch64 sim load/store multiple instruction fixes

[Jim Wilson]

This is my second big load/store patch,and hopefully the last one I
need.  This makes the ldn/stn multiple instructions work correctly.
ld2 loads data into the first reg then the second reg.  ld1 with 2
registers loads data into one lane at a time in the register pair,
alternating between the regs until the lanes are filled.  The
simulator got this wrong, and this patch fixes it, which requires a
large change to the vector load and store code.

The new testcases fail without the patch, and work with the patch.
The GCC C testsuite unexpected failures drop from 1427 to 1295 (-132).

While writing the new testcases, I noticed I had been sloppy about
aligning data in the testcases, and tried to clean that up a bit.  I
may need some further fixes here, but at least every testcase with
data has an alignment directive now.  Also, I noticed bad ldr
instructions in the stn_single.s testcase, where I was loading 128-bit
values and then adding 8 to the address instead of 16.  This fix
changes the input data, and hence requires adjusting the compare
values to make the testcase work again.  There is also one testcase
where I was aligning data but had no data to align, so I removed the
alignment.

Jim
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