Commit: AArch64: Fix simulation of ADDP, FADDP, LD1, CCMP and CCMN

Nick Clifton nickc@redhat.com
Thu Mar 3 15:14:00 GMT 2016


Hi Guys,

  I am checking in the patch below to fix a couple of bugs in the
  AArch64 simulator.  The ADDP and FADDP emulations did not allow for
  the destination register being the same as one or both of the source
  registers.  The LD1 instruction was using the wrong stride value for
  the post-increment of the address, and the CCMP and CCMN emulations
  had inverted the sense of bit 30.

  This fixes 8 unexpected failures in the gcc-dg testsuite.

Cheers
  Nick

sim/aarch64/ChangeLog
2016-03-03  Nick Clifton  <nickc@redhat.com>

	* simulator.c (set_flags_for_sub32): Correct type of signbit.
	(CondCompare): Swap interpretation of bit 30.
	(DO_ADDP): Delete macro.
	(do_vec_ADDP): Copy source registers before starting to update
	destination register.
	(do_vec_FADDP): Likewise.
	(do_vec_load_store): Fix computation of sizeof_operation.
	(rbit64): Fix type of constant.
	(aarch64_step): When displaying insn value, display all 32 bits.

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