[PATCH 2/2 v2] [AArch64] Recognize STR instruction in prologue
Pedro Alves
palves@redhat.com
Thu Dec 1 13:07:00 GMT 2016
Hi Yao,
On 12/01/2016 11:16 AM, Yao Qi wrote:
> + else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
> + || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
> + && (inst.opcode->op == OP_STR_POS
> + || inst.opcode->op == OP_STRF_POS)))
> + && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
> + && strcmp ("str", inst.opcode->name) == 0)
> + {
> + /* STR (immediate) */
> + unsigned int rt = inst.operands[0].reg.regno;
> + int32_t imm = inst.operands[1].addr.offset.imm;
> + unsigned rn = inst.operands[1].addr.base_regno;
Mixed "unsigned int" vs "unsigned" style.
> + int is64
"bool".
> + = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
> + gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
> + || inst.operands[0].type == AARCH64_OPND_Ft);
> +
> + if (inst.operands[0].type == AARCH64_OPND_Ft)
> + {
> + /* Only bottom 64-bit of each V register (D register) need
> + to be preserved. */
> + gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
> + rt += AARCH64_X_REGISTER_COUNT;
> + }
> +
> + pv_area_store (stack, pv_add_constant (regs[rn], imm),
> + is64 ? 8 : 4, regs[rt]);
> + if (inst.operands[1].addr.writeback)
> + regs[rn] = pv_add_constant (regs[rn], imm);
> + }
> else if (inst.opcode->iclass == testbranch)
> {
> /* Stop analysis on branch. */
> @@ -546,6 +575,52 @@ aarch64_analyze_prologue_test (void)
> == -1);
> }
> }
> +
> + /* Test a prologue in which STR is used and frame pointer is not
> + used. */
Thanks for the new comments. This helps.
> + {
> + struct aarch64_prologue_cache cache;
> + cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
> +
> + const uint32_t insns[] = {
"static const". Sorry, my fault.
Othewrise, code-style-wise LGTM. Thanks much for updating.
I've not payed attention to Aarch64-specifics, TBC. I just
assume you got those right. :-)
Thanks,
Pedro Alves
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