[PATCH 00/22] Update of the SPARC SIS simulator

[Mike Frysinger]

On 17 Feb 2015 08:44, Jiri Gaisler wrote:
> This is a 22-part patch that brings the sis simulator into working
> order, and adds support for emulation of the leon2 and leon3 cpus.
> 
> The sis simulator was written by me in the mid 90's, to emulate the erc32
> processor (SPARC V7). It was included into gdb by Cygnus (Stan Shebs?),
> and adapted to also emulate the Fujistu Sparlite processor. The simulator
> has not been actively maintained for about 15 years, and suffered some
> bit-rot. It's primary use has been for RTEMS development. The erc32
> processor is now becoming obsolete, and being replaced by leon2 and
> leon3 cpus in many ESA and NASA missions. These patches will
> allow sis to be useful again, and support the newer leon2/3 processor.

it would be nice if there was a testsuite.  how are you verifying things 
continue to work and there are no regressions ?

should be easy to add some basic .s files to verify insns ... lots of examples 
in the testsuite/sim/ subdirs already.
-mike
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