[PATCH] Power: Correct little-endian e500v2 GPR frame offsets
Stan Shebs
stanshebs@earthlink.net
Thu Mar 6 19:08:00 GMT 2014
On 2/28/14 4:02 PM, Maciej W. Rozycki wrote:
> Hi,
>
> This change corrects GPR frame offset calculation for the e500v2
> processor. On this target, featuring the SPE APU, GPRs are 64-bit and are
> held in stack frames whole with the use of `evstdd' and `evldd'
> instructions. Their integer 32-bit part occupies the low-order word and
> therefore its offset varies between the two endiannesses possible. Code
> in rs6000_frame_cache however assumes the big endianness and
> unconditionally uses an offset of 4 from the address of the whole 64-bit
> quantity in memory. This causes a failure in little-endian testing:
>
>
> OK to apply?
This is OK, with one little request:
> + CORE_ADDR off = byte_order == BFD_ENDIAN_BIG ? 4 : 0;
I don't think there's a rule about this, but it's a little less
confusing to have the conditional expression in a set of parens.
(Empirically, the sources tend to favor parens, but it's not
an overwhelming ratio.)
Stan
stan@codesourcery.com
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