[PATCH] MIPS: Handle the DSP registers for bare metal

[Pedro Alves]

On 12/19/2014 03:54 AM, Yao Qi wrote:
> Pedro Alves <palves@redhat.com> writes:
> 
>> Took me a bit to grok this, but this is adding slack for ACXn, right?
> 
> Sorry, what do you mean by "slack" here?  Is it "gap" or something else?

Yes, "gap".

> The offsets of DSP registers are different on linux and bare metal, so
> this patch gives the correct offset or layout to them.

The proper solution for this issue is to decouple GDB's internal
register numbers from the target's g/G packet layout, which is exactly
what happens when you have a description -- GDB uses the offsets found
in the target description.  And you're touching code that is parsing a
description, so the real issue should be in the target description.

> 
>> But it seems like nothing in GDB knows about those ACX registers.  I
>> guess I'm being dense, but why is this patch needed then?  They should still
>> be accessible to the user even without this change, right?  Assuming the
>> description is including them.
> 
> We want the number of these registers are fixed, and these fixed numbers
> will be used in a follow-up patch about dynamic registers discovery
> (which is about reading available config registers and parsing bits in them)
> MIPS architecture defines 50+ subset of optional CP0 registers, so the
> number of variants is too high to make current static register
> description approach useless.

I think this should be discussed further.

Thanks,
Pedro Alves