[PATCH 2/3] Move mips hardware watchpoint stuff to common/
Yao Qi
yao@codesourcery.com
Thu May 30 02:44:00 GMT 2013
This patch moves the mips-linux hardware watchpoint registers manipulation to
common/mips-linux-watch.[c,h], so that GDBserver can make use of them to avoid
duplication. Some external functions are moved and renamed with prefix
'mips_linux_watch_'.
gdb:
2013-05-30 Yao Qi <yao@codesourcery.com>
* Makefile.in (HFILES_NO_SRCDIR): Add common/mips-linux-watch.h.
(mips-linux-watch.o): New rule.
* common/mips-linux-watch.c, common/mips-linux-watch.h: New.
* config/mips/linux.mh (NAT_FILE): Add mips-linux-watch.o.
* mips-linux-nat.c: Include mips-linux-watch.h.
(W_BIT, R_BIT, I_BIT, W_MASK, R_MASK, I_MASK, IRW_MASK): Move
to common/mips-linux-watch.h.
(MAX_DEBUG_REGISTER): Likewise.
(struct mips_watchpoint): Likewise.
(get_irw_mask, get_reg_mask, get_num_valid, get_watchlo): Move to
to common/mips-linux-watch.c and add name prefix 'mips_linux_watch_'.
(set_watchlo, get_watchhi, set_watchhi, type_to_irw): Likewise.
(populate_regs_from_watches): Likewise.
(mips_linux_read_watch_registers): Move to common/mips-linux-watch.c.
(fill_mask, try_one_watch): Likewise.
(mips_linux_can_use_hw_breakpoint): Caller update.
(mips_linux_stopped_by_watchpoint): Likewise.
(mips_linux_stopped_data_address): Likewise.
(mips_linux_region_ok_for_hw_watchpoint): Likewise.
(mips_linux_new_thread): Likewise.
(mips_linux_insert_watchpoint): Likewise.
(mips_linux_remove_watchpoint): Likewise.
---
gdb/Makefile.in | 6 +-
gdb/common/mips-linux-watch.c | 358 ++++++++++++++++++++++++++++++++++++++
gdb/common/mips-linux-watch.h | 76 ++++++++
gdb/config/mips/linux.mh | 2 +-
gdb/mips-linux-nat.c | 386 ++++-------------------------------------
5 files changed, 473 insertions(+), 355 deletions(-)
create mode 100644 gdb/common/mips-linux-watch.c
create mode 100644 gdb/common/mips-linux-watch.h
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index a6336a2..5fc93e7 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -783,7 +783,7 @@ LINTFILES = $(SFILES) $(YYFILES) $(CONFIG_SRCS) init.c
HFILES_NO_SRCDIR = \
common/gdb_signals.h common/gdb_thread_db.h common/gdb_vecs.h \
-common/i386-xstate.h common/linux-ptrace.h \
+common/i386-xstate.h common/linux-ptrace.h common/mips-linux-watch.h \
proc-utils.h aarch64-tdep.h arm-tdep.h ax-gdb.h ppcfbsd-tdep.h \
ppcnbsd-tdep.h cli-out.h gdb_expat.h breakpoint.h infcall.h obsd-tdep.h \
exec.h m32r-tdep.h osabi.h gdbcore.h solib-som.h amd64bsd-nat.h \
@@ -2009,6 +2009,10 @@ linux-btrace.o: ${srcdir}/common/linux-btrace.c
$(COMPILE) $(srcdir)/common/linux-btrace.c
$(POSTCOMPILE)
+mips-linux-watch.o: ${srcdir}/common/mips-linux-watch.c
+ $(COMPILE) $(srcdir)/common/mips-linux-watch.c
+ $(POSTCOMPILE)
+
#
# gdb/tui/ dependencies
#
diff --git a/gdb/common/mips-linux-watch.c b/gdb/common/mips-linux-watch.c
new file mode 100644
index 0000000..c42e6ef
--- /dev/null
+++ b/gdb/common/mips-linux-watch.c
@@ -0,0 +1,358 @@
+/* Copyright (C) 2009-2013 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include <sys/ptrace.h>
+#include "mips-linux-watch.h"
+#include "gdb_assert.h"
+
+#ifdef GDBSERVER
+#define hw_write '2'
+#define hw_read '3'
+#define hw_access '4'
+#else
+#include "breakpoint.h"
+#endif
+
+/* Assuming usable watch registers REGS, return the num_valid. */
+
+uint32_t
+mips_linux_watch_get_num_valid (struct pt_watch_regs *regs)
+{
+ switch (regs->style)
+ {
+ case pt_watch_style_mips32:
+ return regs->mips32.num_valid;
+ case pt_watch_style_mips64:
+ return regs->mips64.num_valid;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unrecognized watch register style"));
+ }
+}
+
+/* Assuming usable watch registers REGS, return the irw_mask of
+ register N. */
+
+uint32_t
+mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs, int n)
+{
+ switch (regs->style)
+ {
+ case pt_watch_style_mips32:
+ return regs->mips32.watch_masks[n] & IRW_MASK;
+ case pt_watch_style_mips64:
+ return regs->mips64.watch_masks[n] & IRW_MASK;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unrecognized watch register style"));
+ }
+}
+/* Assuming usable watch registers REGS, return the watchlo of
+ register N. */
+
+CORE_ADDR
+mips_linux_watch_get_watchlo (struct pt_watch_regs *regs, int n)
+{
+ switch (regs->style)
+ {
+ case pt_watch_style_mips32:
+ return regs->mips32.watchlo[n];
+ case pt_watch_style_mips64:
+ return regs->mips64.watchlo[n];
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unrecognized watch register style"));
+ }
+}
+
+/* Assuming usable watch registers REGS, set a watchlo VALUE of
+ register N. */
+
+void
+mips_linux_watch_set_watchlo (struct pt_watch_regs *regs, int n,
+ CORE_ADDR value)
+{
+ switch (regs->style)
+ {
+ case pt_watch_style_mips32:
+ /* The cast will never throw away bits as 64 bit addresses can
+ never be used on a 32 bit kernel. */
+ regs->mips32.watchlo[n] = (uint32_t)value;
+ break;
+ case pt_watch_style_mips64:
+ regs->mips64.watchlo[n] = value;
+ break;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unrecognized watch register style"));
+ }
+}
+
+/* Assuming usable watch registers REGS, return the watchhi of
+ register N. */
+
+uint32_t
+mips_linux_watch_get_watchhi (struct pt_watch_regs *regs, int n)
+{
+ switch (regs->style)
+ {
+ case pt_watch_style_mips32:
+ return regs->mips32.watchhi[n];
+ case pt_watch_style_mips64:
+ return regs->mips64.watchhi[n];
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unrecognized watch register style"));
+ }
+}
+
+/* Assuming usable watch registers REGS, set a watchhi VALUE of
+ register N. */
+
+void
+mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n,
+ uint16_t value)
+{
+ switch (regs->style)
+ {
+ case pt_watch_style_mips32:
+ regs->mips32.watchhi[n] = value;
+ break;
+ case pt_watch_style_mips64:
+ regs->mips64.watchhi[n] = value;
+ break;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unrecognized watch register style"));
+ }
+}
+
+/* Set any low order bits in MASK that are not set. */
+
+static CORE_ADDR
+fill_mask (CORE_ADDR mask)
+{
+ CORE_ADDR f = 1;
+ while (f && f < mask)
+ {
+ mask |= f;
+ f <<= 1;
+ }
+ return mask;
+}
+
+/* Assuming usable watch registers REGS, return the reg_mask of
+ register N. */
+
+static uint32_t
+get_reg_mask (struct pt_watch_regs *regs, int n)
+{
+ switch (regs->style)
+ {
+ case pt_watch_style_mips32:
+ return regs->mips32.watch_masks[n] & ~IRW_MASK;
+ case pt_watch_style_mips64:
+ return regs->mips64.watch_masks[n] & ~IRW_MASK;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unrecognized watch register style"));
+ }
+}
+
+/* Try to add a single watch to the specified registers REGS. The
+ address of added watch is ADDR, the length is LEN, and the mask
+ is IRW. Return 1 on success, 0 on failure. */
+
+int
+mips_linux_watch_try_one_watch (struct pt_watch_regs *regs,
+ CORE_ADDR addr, int len, unsigned irw)
+{
+ CORE_ADDR base_addr, last_byte, break_addr, segment_len;
+ CORE_ADDR mask_bits, t_low;
+ uint16_t t_hi;
+ int i, free_watches;
+ struct pt_watch_regs regs_copy;
+
+ if (len <= 0)
+ return 0;
+
+ last_byte = addr + len - 1;
+ mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
+ base_addr = addr & ~mask_bits;
+
+ /* Check to see if it is covered by current registers. */
+ for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
+ {
+ t_low = mips_linux_watch_get_watchlo (regs, i);
+ if (t_low != 0 && irw == ((unsigned) t_low & irw))
+ {
+ t_hi = mips_linux_watch_get_watchhi (regs, i) | IRW_MASK;
+ t_low &= ~(CORE_ADDR) t_hi;
+ if (addr >= t_low && last_byte <= (t_low + t_hi))
+ return 1;
+ }
+ }
+ /* Try to find an empty register. */
+ free_watches = 0;
+ for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
+ {
+ t_low = mips_linux_watch_get_watchlo (regs, i);
+ if (t_low == 0
+ && irw == (mips_linux_watch_get_irw_mask (regs, i) & irw))
+ {
+ if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
+ {
+ /* It fits, we'll take it. */
+ mips_linux_watch_set_watchlo (regs, i, base_addr | irw);
+ mips_linux_watch_set_watchhi (regs, i,
+ mask_bits & ~IRW_MASK);
+ return 1;
+ }
+ else
+ {
+ /* It doesn't fit, but has the proper IRW capabilities. */
+ free_watches++;
+ }
+ }
+ }
+ if (free_watches > 1)
+ {
+ /* Try to split it across several registers. */
+ regs_copy = *regs;
+ for (i = 0;
+ i < mips_linux_watch_get_num_valid (®s_copy);
+ i++)
+ {
+ t_low = mips_linux_watch_get_watchlo (®s_copy, i);
+ t_hi = get_reg_mask (®s_copy, i) | IRW_MASK;
+ if (t_low == 0 && irw == (t_hi & irw))
+ {
+ t_low = addr & ~(CORE_ADDR) t_hi;
+ break_addr = t_low + t_hi + 1;
+ if (break_addr >= addr + len)
+ segment_len = len;
+ else
+ segment_len = break_addr - addr;
+ mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
+ mips_linux_watch_set_watchlo (®s_copy, i,
+ (addr & ~mask_bits) | irw);
+ mips_linux_watch_set_watchhi (®s_copy, i,
+ mask_bits & ~IRW_MASK);
+ if (break_addr >= addr + len)
+ {
+ *regs = regs_copy;
+ return 1;
+ }
+ len = addr + len - break_addr;
+ addr = break_addr;
+ }
+ }
+ }
+ /* It didn't fit anywhere, we failed. */
+ return 0;
+}
+
+/* Convert GDB's TYPE to an IRW mask. */
+
+unsigned
+mips_linux_watch_type_to_irw (int type)
+{
+ switch (type)
+ {
+ case hw_write:
+ return W_MASK;
+ case hw_read:
+ return R_MASK;
+ case hw_access:
+ return (W_MASK | R_MASK);
+ default:
+ return 0;
+ }
+}
+
+/* Fill in the watch registers REGS with the currently cached
+ watches CURRENT_WATCHES. */
+
+void
+mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches,
+ struct pt_watch_regs *regs)
+{
+ struct mips_watchpoint *w;
+ int i;
+
+ /* Clear them out. */
+ for (i = 0; i < mips_linux_watch_get_num_valid (regs); i++)
+ {
+ mips_linux_watch_set_watchlo (regs, i, 0);
+ mips_linux_watch_set_watchhi (regs, i, 0);
+ }
+
+ w = current_watches;
+ while (w)
+ {
+ unsigned irw = mips_linux_watch_type_to_irw (w->type);
+
+ i = mips_linux_watch_try_one_watch (regs, w->addr, w->len, irw);
+ /* They must all fit, because we previously calculated that they
+ would. */
+ gdb_assert (i);
+ w = w->next;
+ }
+}
+
+/* Read the watch registers of process LWPID and store it in
+ WATCH_READBACK. Save true to *WATCH_READBACK_VALID if watch
+ registers are valid. Return 1 if watch registers are usable.
+ Cached information is used unless FORCE is true. */
+
+int
+mips_linux_read_watch_registers (long lwpid,
+ struct pt_watch_regs *watch_readback,
+ int *watch_readback_valid, int force)
+{
+ if (force || *watch_readback_valid == 0)
+ {
+ if (ptrace (PTRACE_GET_WATCH_REGS, lwpid, watch_readback) == -1)
+ {
+ *watch_readback_valid = -1;
+ return 0;
+ }
+ switch (watch_readback->style)
+ {
+ case pt_watch_style_mips32:
+ if (watch_readback->mips32.num_valid == 0)
+ {
+ *watch_readback_valid = -1;
+ return 0;
+ }
+ break;
+ case pt_watch_style_mips64:
+ if (watch_readback->mips64.num_valid == 0)
+ {
+ *watch_readback_valid = -1;
+ return 0;
+ }
+ break;
+ default:
+ *watch_readback_valid = -1;
+ return 0;
+ }
+ /* Watch registers appear to be usable. */
+ *watch_readback_valid = 1;
+ }
+ return (*watch_readback_valid == 1) ? 1 : 0;
+}
diff --git a/gdb/common/mips-linux-watch.h b/gdb/common/mips-linux-watch.h
new file mode 100644
index 0000000..5d4fa00
--- /dev/null
+++ b/gdb/common/mips-linux-watch.h
@@ -0,0 +1,76 @@
+/* Copyright (C) 2009-2013 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef MIPS_LINUX_WATCH_H
+#define MIPS_LINUX_WATCH_H 1
+
+#ifdef GDBSERVER
+#include "server.h"
+#else
+#include "defs.h"
+#endif
+
+#include <asm/ptrace.h>
+#include <stdint.h>
+
+#define W_BIT 0
+#define R_BIT 1
+#define I_BIT 2
+
+#define W_MASK (1 << W_BIT)
+#define R_MASK (1 << R_BIT)
+#define I_MASK (1 << I_BIT)
+
+#define IRW_MASK (I_MASK | R_MASK | W_MASK)
+
+#define MAX_DEBUG_REGISTER 8
+
+/* We keep list of all watchpoints we should install and calculate the
+ watch register values each time the list changes. This allows for
+ easy sharing of watch registers for more than one watchpoint. */
+
+struct mips_watchpoint
+{
+ CORE_ADDR addr;
+ int len;
+ int type;
+ struct mips_watchpoint *next;
+};
+
+uint32_t mips_linux_watch_get_num_valid (struct pt_watch_regs *regs);
+uint32_t mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs,
+ int set);
+CORE_ADDR mips_linux_watch_get_watchlo (struct pt_watch_regs *regs,
+ int set);
+void mips_linux_watch_set_watchlo (struct pt_watch_regs *regs,
+ int set, CORE_ADDR value);
+uint32_t mips_linux_watch_get_watchhi (struct pt_watch_regs *regs,
+ int n);
+void mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n,
+ uint16_t value);
+int mips_linux_watch_try_one_watch (struct pt_watch_regs *regs,
+ CORE_ADDR addr, int len,
+ unsigned irw);
+void mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches,
+ struct pt_watch_regs *regs);
+unsigned mips_linux_watch_type_to_irw (int type);
+
+int mips_linux_read_watch_registers (long lwpid,
+ struct pt_watch_regs *watch_readback,
+ int *watch_readback_valid,
+ int force);
+#endif
diff --git a/gdb/config/mips/linux.mh b/gdb/config/mips/linux.mh
index 2f8e5dd..a4f23e3 100644
--- a/gdb/config/mips/linux.mh
+++ b/gdb/config/mips/linux.mh
@@ -3,7 +3,7 @@ NAT_FILE= config/nm-linux.h
NATDEPFILES= inf-ptrace.o fork-child.o mips-linux-nat.o \
linux-thread-db.o proc-service.o \
linux-nat.o linux-osdata.o linux-fork.o \
- linux-procfs.o linux-ptrace.o
+ linux-procfs.o linux-ptrace.o mips-linux-watch.o
NAT_CDEPS = $(srcdir)/proc-service.list
LOADLIBES = -ldl $(RDYNAMIC)
diff --git a/gdb/mips-linux-nat.c b/gdb/mips-linux-nat.c
index d8b4d29..b782657 100644
--- a/gdb/mips-linux-nat.c
+++ b/gdb/mips-linux-nat.c
@@ -34,6 +34,7 @@
#include <sgidefs.h>
#include <sys/ptrace.h>
+#include "mips-linux-watch.h"
#include <asm/ptrace.h>
#include "features/mips-linux.c"
@@ -469,18 +470,6 @@ mips_linux_read_description (struct target_ops *ops)
# define PTRACE_SET_WATCH_REGS 0xd1
#endif
-#define W_BIT 0
-#define R_BIT 1
-#define I_BIT 2
-
-#define W_MASK (1 << W_BIT)
-#define R_MASK (1 << R_BIT)
-#define I_MASK (1 << I_BIT)
-
-#define IRW_MASK (I_MASK | R_MASK | W_MASK)
-
-#define MAX_DEBUG_REGISTER 8
-
/* -1 if the kernel and/or CPU do not support watch registers.
1 if watch_readback is valid and we can read style, num_valid
and the masks.
@@ -492,18 +481,6 @@ static int watch_readback_valid;
static struct pt_watch_regs watch_readback;
-/* We keep list of all watchpoints we should install and calculate the
- watch register values each time the list changes. This allows for
- easy sharing of watch registers for more than one watchpoint. */
-
-struct mips_watchpoint
-{
- CORE_ADDR addr;
- int len;
- int type;
- struct mips_watchpoint *next;
-};
-
static struct mips_watchpoint *current_watches;
/* The current set of watch register values for writing the
@@ -511,131 +488,6 @@ static struct mips_watchpoint *current_watches;
static struct pt_watch_regs watch_mirror;
-/* Assuming usable watch registers, return the irw_mask. */
-
-static uint32_t
-get_irw_mask (struct pt_watch_regs *regs, int set)
-{
- switch (regs->style)
- {
- case pt_watch_style_mips32:
- return regs->mips32.watch_masks[set] & IRW_MASK;
- case pt_watch_style_mips64:
- return regs->mips64.watch_masks[set] & IRW_MASK;
- default:
- internal_error (__FILE__, __LINE__,
- _("Unrecognized watch register style"));
- }
-}
-
-/* Assuming usable watch registers, return the reg_mask. */
-
-static uint32_t
-get_reg_mask (struct pt_watch_regs *regs, int set)
-{
- switch (regs->style)
- {
- case pt_watch_style_mips32:
- return regs->mips32.watch_masks[set] & ~IRW_MASK;
- case pt_watch_style_mips64:
- return regs->mips64.watch_masks[set] & ~IRW_MASK;
- default:
- internal_error (__FILE__, __LINE__,
- _("Unrecognized watch register style"));
- }
-}
-
-/* Assuming usable watch registers, return the num_valid. */
-
-static uint32_t
-get_num_valid (struct pt_watch_regs *regs)
-{
- switch (regs->style)
- {
- case pt_watch_style_mips32:
- return regs->mips32.num_valid;
- case pt_watch_style_mips64:
- return regs->mips64.num_valid;
- default:
- internal_error (__FILE__, __LINE__,
- _("Unrecognized watch register style"));
- }
-}
-
-/* Assuming usable watch registers, return the watchlo. */
-
-static CORE_ADDR
-get_watchlo (struct pt_watch_regs *regs, int set)
-{
- switch (regs->style)
- {
- case pt_watch_style_mips32:
- return regs->mips32.watchlo[set];
- case pt_watch_style_mips64:
- return regs->mips64.watchlo[set];
- default:
- internal_error (__FILE__, __LINE__,
- _("Unrecognized watch register style"));
- }
-}
-
-/* Assuming usable watch registers, set a watchlo value. */
-
-static void
-set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value)
-{
- switch (regs->style)
- {
- case pt_watch_style_mips32:
- /* The cast will never throw away bits as 64 bit addresses can
- never be used on a 32 bit kernel. */
- regs->mips32.watchlo[set] = (uint32_t)value;
- break;
- case pt_watch_style_mips64:
- regs->mips64.watchlo[set] = value;
- break;
- default:
- internal_error (__FILE__, __LINE__,
- _("Unrecognized watch register style"));
- }
-}
-
-/* Assuming usable watch registers, return the watchhi. */
-
-static uint32_t
-get_watchhi (struct pt_watch_regs *regs, int n)
-{
- switch (regs->style)
- {
- case pt_watch_style_mips32:
- return regs->mips32.watchhi[n];
- case pt_watch_style_mips64:
- return regs->mips64.watchhi[n];
- default:
- internal_error (__FILE__, __LINE__,
- _("Unrecognized watch register style"));
- }
-}
-
-/* Assuming usable watch registers, set a watchhi value. */
-
-static void
-set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value)
-{
- switch (regs->style)
- {
- case pt_watch_style_mips32:
- regs->mips32.watchhi[n] = value;
- break;
- case pt_watch_style_mips64:
- regs->mips64.watchhi[n] = value;
- break;
- default:
- internal_error (__FILE__, __LINE__,
- _("Unrecognized watch register style"));
- }
-}
-
static void
mips_show_dr (const char *func, CORE_ADDR addr,
int len, enum target_hw_bp_type type)
@@ -656,69 +508,11 @@ mips_show_dr (const char *func, CORE_ADDR addr,
for (i = 0; i < MAX_DEBUG_REGISTER; i++)
printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
paddress (target_gdbarch (),
- get_watchlo (&watch_mirror, i)),
+ mips_linux_watch_get_watchlo (&watch_mirror,
+ i)),
paddress (target_gdbarch (),
- get_watchhi (&watch_mirror, i)));
-}
-
-/* Return 1 if watch registers are usable. Cached information is used
- unless force is true. */
-
-static int
-mips_linux_read_watch_registers (int force)
-{
- int tid;
-
- if (force || watch_readback_valid == 0)
- {
- tid = ptid_get_lwp (inferior_ptid);
- if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1)
- {
- watch_readback_valid = -1;
- return 0;
- }
- switch (watch_readback.style)
- {
- case pt_watch_style_mips32:
- if (watch_readback.mips32.num_valid == 0)
- {
- watch_readback_valid = -1;
- return 0;
- }
- break;
- case pt_watch_style_mips64:
- if (watch_readback.mips64.num_valid == 0)
- {
- watch_readback_valid = -1;
- return 0;
- }
- break;
- default:
- watch_readback_valid = -1;
- return 0;
- }
- /* Watch registers appear to be usable. */
- watch_readback_valid = 1;
- }
- return (watch_readback_valid == 1) ? 1 : 0;
-}
-
-/* Convert GDB's type to an IRW mask. */
-
-static unsigned
-type_to_irw (int type)
-{
- switch (type)
- {
- case hw_write:
- return W_MASK;
- case hw_read:
- return R_MASK;
- case hw_access:
- return (W_MASK | R_MASK);
- default:
- return 0;
- }
+ mips_linux_watch_get_watchhi (&watch_mirror,
+ i)));
}
/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
@@ -730,7 +524,9 @@ mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
int i;
uint32_t wanted_mask, irw_mask;
- if (!mips_linux_read_watch_registers (0))
+ if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
+ &watch_readback,
+ &watch_readback_valid, 0))
return 0;
switch (type)
@@ -748,9 +544,11 @@ mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
return 0;
}
- for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++)
+ for (i = 0;
+ i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
+ i++)
{
- irw_mask = get_irw_mask (&watch_readback, i);
+ irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
if ((irw_mask & wanted_mask) == wanted_mask)
cnt--;
}
@@ -767,13 +565,15 @@ mips_linux_stopped_by_watchpoint (void)
int n;
int num_valid;
- if (!mips_linux_read_watch_registers (1))
+ if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
+ &watch_readback,
+ &watch_readback_valid, 1))
return 0;
- num_valid = get_num_valid (&watch_readback);
+ num_valid = mips_linux_watch_get_num_valid (&watch_readback);
for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
- if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
+ if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
return 1;
return 0;
@@ -791,106 +591,6 @@ mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr)
return 0;
}
-/* Set any low order bits in mask that are not set. */
-
-static CORE_ADDR
-fill_mask (CORE_ADDR mask)
-{
- CORE_ADDR f = 1;
- while (f && f < mask)
- {
- mask |= f;
- f <<= 1;
- }
- return mask;
-}
-
-/* Try to add a single watch to the specified registers. Return 1 on
- success, 0 on failure. */
-
-static int
-try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr,
- int len, unsigned irw)
-{
- CORE_ADDR base_addr, last_byte, break_addr, segment_len;
- CORE_ADDR mask_bits, t_low, t_low_end;
- uint16_t t_hi;
- int i, free_watches;
- struct pt_watch_regs regs_copy;
-
- if (len <= 0)
- return 0;
-
- last_byte = addr + len - 1;
- mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK;
- base_addr = addr & ~mask_bits;
-
- /* Check to see if it is covered by current registers. */
- for (i = 0; i < get_num_valid (regs); i++)
- {
- t_low = get_watchlo (regs, i);
- if (t_low != 0 && irw == ((unsigned)t_low & irw))
- {
- t_hi = get_watchhi (regs, i) | IRW_MASK;
- t_low &= ~(CORE_ADDR)t_hi;
- if (addr >= t_low && last_byte <= (t_low + t_hi))
- return 1;
- }
- }
- /* Try to find an empty register. */
- free_watches = 0;
- for (i = 0; i < get_num_valid (regs); i++)
- {
- t_low = get_watchlo (regs, i);
- if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw))
- {
- if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK))
- {
- /* It fits, we'll take it. */
- set_watchlo (regs, i, base_addr | irw);
- set_watchhi (regs, i, mask_bits & ~IRW_MASK);
- return 1;
- }
- else
- {
- /* It doesn't fit, but has the proper IRW capabilities. */
- free_watches++;
- }
- }
- }
- if (free_watches > 1)
- {
- /* Try to split it across several registers. */
- regs_copy = *regs;
- for (i = 0; i < get_num_valid (®s_copy); i++)
- {
- t_low = get_watchlo (®s_copy, i);
- t_hi = get_reg_mask (®s_copy, i) | IRW_MASK;
- if (t_low == 0 && irw == (t_hi & irw))
- {
- t_low = addr & ~(CORE_ADDR)t_hi;
- break_addr = t_low + t_hi + 1;
- if (break_addr >= addr + len)
- segment_len = len;
- else
- segment_len = break_addr - addr;
- mask_bits = fill_mask (addr ^ (addr + segment_len - 1));
- set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw);
- set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK);
- if (break_addr >= addr + len)
- {
- *regs = regs_copy;
- return 1;
- }
- len = addr + len - break_addr;
- addr = break_addr;
- }
- }
- }
- /* It didn't fit anywhere, we failed. */
- return 0;
-}
-
/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
the specified region can be covered by the watch registers. */
@@ -900,17 +600,18 @@ mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
struct pt_watch_regs dummy_regs;
int i;
- if (!mips_linux_read_watch_registers (0))
+ if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
+ &watch_readback,
+ &watch_readback_valid, 0))
return 0;
dummy_regs = watch_readback;
/* Clear them out. */
- for (i = 0; i < get_num_valid (&dummy_regs); i++)
- set_watchlo (&dummy_regs, i, 0);
- return try_one_watch (&dummy_regs, addr, len, 0);
+ for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
+ mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
+ return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
}
-
/* Write the mirrored watch register values for each thread. */
static int
@@ -936,7 +637,9 @@ mips_linux_new_thread (struct lwp_info *lp)
{
int tid;
- if (!mips_linux_read_watch_registers (0))
+ if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
+ &watch_readback,
+ &watch_readback_valid, 0))
return;
tid = ptid_get_lwp (lp->ptid);
@@ -944,32 +647,6 @@ mips_linux_new_thread (struct lwp_info *lp)
perror_with_name (_("Couldn't write debug register"));
}
-/* Fill in the watch registers with the currently cached watches. */
-
-static void
-populate_regs_from_watches (struct pt_watch_regs *regs)
-{
- struct mips_watchpoint *w;
- int i;
-
- /* Clear them out. */
- for (i = 0; i < get_num_valid (regs); i++)
- {
- set_watchlo (regs, i, 0);
- set_watchhi (regs, i, 0);
- }
-
- w = current_watches;
- while (w)
- {
- i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type));
- /* They must all fit, because we previously calculated that they
- would. */
- gdb_assert (i);
- w = w->next;
- }
-}
-
/* Target to_insert_watchpoint implementation. Try to insert a new
watch. Return zero on success. */
@@ -984,7 +661,9 @@ mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
int i;
int retval;
- if (!mips_linux_read_watch_registers (0))
+ if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
+ &watch_readback,
+ &watch_readback_valid, 0))
return -1;
if (len <= 0)
@@ -992,10 +671,11 @@ mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type,
regs = watch_readback;
/* Add the current watches. */
- populate_regs_from_watches (®s);
+ mips_linux_watch_populate_regs (current_watches, ®s);
/* Now try to add the new watch. */
- if (!try_one_watch (®s, addr, len, type_to_irw (type)))
+ if (!mips_linux_watch_try_one_watch (®s, addr, len,
+ mips_linux_watch_type_to_irw (type)))
return -1;
/* It fit. Stick it on the end of the list. */
@@ -1057,7 +737,7 @@ mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type,
gdb_assert (watch_readback_valid == 1);
watch_mirror = watch_readback;
- populate_regs_from_watches (&watch_mirror);
+ mips_linux_watch_populate_regs (current_watches, &watch_mirror);
retval = write_watchpoint_regs ();
--
1.7.7.6
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