[PATCH] sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set

[Mike Frysinger]

From: Robin Getz <robin.getz@analog.com>

The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2011-03-21  Robin Getz  <robin.getz@analog.com>

	* bfin-sim.c (decode_dsp32shift_0): Set acc0 to the unextended
	value for the VIT_MAX insn, and mask off the result when done.
---
 sim/bfin/bfin-sim.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 42c9c55..3916fad 100644
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -5437,7 +5437,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
     }
   else if ((sop == 0 || sop == 1) && sopcde == 9)
     {
-      bs40 acc0 = get_extended_acc (cpu, 0);
+      bs40 acc0 = get_unextended_acc (cpu, 0);
       bs16 sL, sH, out;
 
       TRACE_INSN (cpu, "R%i.L = VIT_MAX (R%i) (AS%c);",
@@ -5447,7 +5447,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       sH = DREG (src1) >> 16;
 
       if (sop & 1)
-	acc0 >>= 1;
+	acc0 = (acc0 & 0xfeffffffffull) >> 1;
       else
 	acc0 <<= 1;
 
-- 
1.7.4.1