[ob] Fix mips64 single step with 64-bit CORE_ADDR

[Daniel Jacobowitz]

Something else I've had lying around.  (addr & ~1) is IIRC harmless
but unclear; however, (addr & 0xf0000000) is obviously harmful.

Tested on mips64-linux and committed as obvious.

-- 
Daniel Jacobowitz
CodeSourcery

2006-03-15  Daniel Jacobowitz  <dan@codesourcery.com>

	* mips-tdep.c (is_mips16_addr, mips32_next_pc, add_offset_16):
	Correct arithmetic for 64-bit CORE_ADDR.

Index: src/gdb/mips-tdep.c
===================================================================
--- src.orig/gdb/mips-tdep.c	2006-03-14 17:05:07.000000000 -0500
+++ src/gdb/mips-tdep.c	2006-03-14 17:14:21.000000000 -0500
@@ -202,7 +202,7 @@ is_mips16_addr (CORE_ADDR addr)
 static CORE_ADDR
 unmake_mips16_addr (CORE_ADDR addr)
 {
-  return ((addr) & ~1);
+  return ((addr) & ~(CORE_ADDR) 1);
 }
 
 /* Return the contents of register REGNUM as a signed integer.  */
@@ -989,14 +989,14 @@ mips32_next_pc (CORE_ADDR pc)
 	    unsigned long reg;
 	    reg = jtype_target (inst) << 2;
 	    /* Upper four bits get never changed... */
-	    pc = reg + ((pc + 4) & 0xf0000000);
+	    pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff);
 	  }
 	  break;
 	  /* FIXME case JALX : */
 	  {
 	    unsigned long reg;
 	    reg = jtype_target (inst) << 2;
-	    pc = reg + ((pc + 4) & 0xf0000000) + 1;	/* yes, +1 */
+	    pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1;	/* yes, +1 */
 	    /* Add 1 to indicate 16 bit mode - Invert ISA mode */
 	  }
 	  break;		/* The new PC will be alternate mode */
@@ -1202,7 +1202,7 @@ unpack_mips16 (CORE_ADDR pc,
 static CORE_ADDR
 add_offset_16 (CORE_ADDR pc, int offset)
 {
-  return ((offset << 2) | ((pc + 2) & (0xf0000000)));
+  return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)));
 }
 
 static CORE_ADDR